公开(公告)号：US09136140B2

公开(公告)日：2015-09-15

申请号：US14025524

申请日：2013-09-12

Applicant: United Microelectronics Corp.

Inventor： Wen-Liang Huang ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L21/00 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3088

Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.

Abstract translation: 提供了图案化方法。 首先，在基板上形成材料层。 此后，在材料层上形成多个定向自组装（DSA）图案。 之后，通过使用单个光刻工艺形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层覆盖DSA图案的第一部分并且暴露DSA图案的第二部分。 此外，通过蚀刻工艺，使用图案化的光致抗蚀剂层和DSA图案的第二部分作为掩模来对材料层进行图案化。

公开(公告)号：US20230262993A1

公开(公告)日：2023-08-17

申请号：US18304335

申请日：2023-04-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US11690230B2

公开(公告)日：2023-06-27

申请号：US17345806

申请日：2021-06-11

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US09653404B1

公开(公告)日：2017-05-16

申请号：US15245161

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Jing Wang ,  En-Chiuan Liou ,  Mei-Chen Chen ,  Han-Lin Zeng ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction.

公开(公告)号：US12089419B2

公开(公告)日：2024-09-10

申请号：US18304335

申请日：2023-04-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US20240122078A1

公开(公告)日：2024-04-11

申请号：US18542791

申请日：2023-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US11895927B2

公开(公告)日：2024-02-06

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US20220344579A1

公开(公告)日：2022-10-27

申请号：US17319106

申请日：2021-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Tang-Chun Weng ,  Cheng-Yi Lin ,  Yung-Shen Chen ,  Chia-Hung Lin

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

公开(公告)号：US20180218917A1

公开(公告)日：2018-08-02

申请号：US15423544

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Hon-Huei Liu ,  Chia-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/66

Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.

公开(公告)号：US20220367565A1

公开(公告)日：2022-11-17

申请号：US17345806

申请日：2021-06-11

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H01L27/22 ,  H01L23/522 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.