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1.发明授权Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory 有权通过删除内存障碍指令并将其包含在采用硬件事务内存的事务中进行代码段优化公开(公告)号：US08972704B2
公开(公告)日：2015-03-03
申请号：US13326320
申请日：2011-12-15
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译： 由计算设备执行的计算机程序的代码部分包括存储器障碍指令。 在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。 可以监视执行代码部分的内容，以便产生监视结果。 如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止所对应的中止阈值，则代码部分被分割为代码子部分，并且每个代码子部分包含在单独的交易中， 采用硬件事务内存。 拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。
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公开(公告)号：US09032190B2
公开(公告)日：2015-05-12
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译： 并行执行前导线程和后退线程。 假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。 此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。 当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。 当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。
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3.发明申请Code optimization by memory barrier removal and enclosure within transaction 有权通过内存障碍去除和事务中的机箱进行代码优化公开(公告)号：US20130159678A1
公开(公告)日：2013-06-20
申请号：US13326320
申请日：2011-12-15
IPC分类号： G06F9/30
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译： 由计算设备执行的计算机程序的代码部分包括存储器障碍指令。 在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。 可以监视执行代码部分的内容，以便产生监视结果。 如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止对应的中止阈值，则代码部分被分割成代码子部分，并且每个代码子部分包含在单独的交易中， 采用硬件事务内存。 拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。
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公开(公告)号：US20110047364A1
公开(公告)日：2011-02-24
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译： 并行执行前导线程和后退线程。 假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。 此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。 当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。 当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。
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5.发明授权公开(公告)号：US08990786B2
公开(公告)日：2015-03-24
申请号：US13307731
申请日：2011-11-30
申请人： Takuya Nakaike
发明人： Takuya Nakaike
IPC分类号： G06F9/45
CPC分类号： G06F8/4443 , G06F8/443 , G06F8/4441 , G06F8/447
摘要： An apparatus having a transactional memory enabling exclusive control to execute a transaction. The apparatus includes: a first code generating unit configured to interpret a program, and generate first code in which a begin instruction to begin a transaction and an end instruction to commit the transaction are inserted before and after an instruction sequence including multiple instructions to execute designated processing in the program; a second code generating unit configured to generate second code at a predetermined timing by using the multiple instructions according to the designated processing; and a code write unit configured to overwrite the instruction sequence of the first code with the second code or to write the second code to a part of the first code in the transaction.
摘要翻译： 具有能够进行交易的排他控制的事务性存储器的装置。 该装置包括：第一代码生成单元，被配置为解释程序，并且生成第一代码，其中开始交易的开始指令和提交交易的结束指令在包括执行指定的多个指令的指令序列之前和之后插入 程序处理; 第二代码生成单元，被配置为通过使用根据指定处理的多个指令在预定定时生成第二代码; 以及代码写入单元，被配置为用第二代码覆盖第一代码的指令序列，或者将第二代码写入事务中的第一代码的一部分。
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公开(公告)号：US20070256066A1
公开(公告)日：2007-11-01
申请号：US11380833
申请日：2006-04-28
IPC分类号： G06F9/45
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译： 提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。 变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。 在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。
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公开(公告)号：US08181169B2
公开(公告)日：2012-05-15
申请号：US12170990
申请日：2008-07-10
申请人： Takuya Nakaike , Hideaki Komacou , Soiichi Kawano
发明人： Takuya Nakaike , Hideaki Komacou , Soiichi Kawano
IPC分类号： G06F9/45
CPC分类号： G06F1/3203 , G06F8/4432 , G06F9/4893 , Y02D10/24 , Y02D10/41
摘要： Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas.
摘要翻译： 通过以比以前更高的精度调整CPU的计算能力来减少与执行程序相关的能量消耗的装置，编译器和方法。 设备为CPU设置适当的计算能力。 其包括：在执行程序执行期间执行包括在执行程序中的多个程序区域中的每一个时，改变CPU的计算能力，并且测量每个程序区域的执行时间; 基于针对相应程序区域测量的每个计算能力的执行时间，确定使用CPU执行程序区域所需的最佳计算能力; 并且对于每个程序区域，执行用于在执行执行程序的过程中再次执行程序区域时执行程序区域的最佳计算能力的设置。
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8.发明授权Data processing and difference computation for generating addressing information 失效用于生成寻址信息的数据处理和差分计算公开(公告)号：US07530014B2
公开(公告)日：2009-05-05
申请号：US10612786
申请日：2003-07-02
申请人： Mari Abe , Teruo Koyanagi , Kohichi Ono , Masahiro Hori , Takuya Nakaike
发明人： Mari Abe , Teruo Koyanagi , Kohichi Ono , Masahiro Hori , Takuya Nakaike
IPC分类号： G06F17/00
CPC分类号： G06F17/2247 , G06F17/2211
摘要： Methods, apparatus and systems to keep a desired element properly addressed in a structured document in which particular elements are addressed, even if the structured document is modified. In an example embodiment, the invention comprises a difference computation unit for computing a difference between structured documents, and an XPath update unit for generating addressing information from addressing information that addresses a part of a particular structured document based on information on the difference computed by the difference computation unit, the generated addressing information addressing a corresponding part of the other structured document.
摘要翻译： 即使修改了结构化文档，方法，装置和系统也可以在特定元素被寻址的结构化文档中保持所需要的元素。 在一个示例性实施例中，本发明包括用于计算结构化文档之间的差异的差分计算单元和用于基于关于由特定结构化文档的一部分计算的差异的信息的寻址信息来生成寻址信息的XPath更新单元 差分计算单元，生成的寻址信息寻址另一结构化文档的对应部分。
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公开(公告)号：US20090055634A1
公开(公告)日：2009-02-26
申请号：US12190466
申请日：2008-08-12
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G06F9/318
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译： 使Web服务器等的响应时间更接近目标值。 控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。 控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作 提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。
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公开(公告)号：US20060095902A1
公开(公告)日：2006-05-04
申请号：US11255027
申请日：2005-10-20
申请人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
发明人： Takuya Nakaike , Hideaki Komatsu , Seiichi Kawano
IPC分类号： G06F9/45
CPC分类号： G06F1/3203 , G06F8/4432 , G06F9/4893 , Y02D10/24 , Y02D10/41
摘要： Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas.
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