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公开(公告)号：US09032190B2
公开(公告)日：2015-05-12
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译： 并行执行前导线程和后退线程。 假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。 此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。 当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。 当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。
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2.发明授权Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory 有权通过删除内存障碍指令并将其包含在采用硬件事务内存的事务中进行代码段优化公开(公告)号：US08972704B2
公开(公告)日：2015-03-03
申请号：US13326320
申请日：2011-12-15
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译： 由计算设备执行的计算机程序的代码部分包括存储器障碍指令。 在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。 可以监视执行代码部分的内容，以便产生监视结果。 如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止所对应的中止阈值，则代码部分被分割为代码子部分，并且每个代码子部分包含在单独的交易中， 采用硬件事务内存。 拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。
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3.发明申请Code optimization by memory barrier removal and enclosure within transaction 有权通过内存障碍去除和事务中的机箱进行代码优化公开(公告)号：US20130159678A1
公开(公告)日：2013-06-20
申请号：US13326320
申请日：2011-12-15
IPC分类号： G06F9/30
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译： 由计算设备执行的计算机程序的代码部分包括存储器障碍指令。 在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。 可以监视执行代码部分的内容，以便产生监视结果。 如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止对应的中止阈值，则代码部分被分割成代码子部分，并且每个代码子部分包含在单独的交易中， 采用硬件事务内存。 拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。
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公开(公告)号：US20110047364A1
公开(公告)日：2011-02-24
申请号：US12859842
申请日：2010-08-20
申请人： Toshihiko Koju , Takuya Nakaike
发明人： Toshihiko Koju , Takuya Nakaike
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/1407 , G06F11/1479 , G06F11/1497 , G06F11/1629 , G06F11/1695
摘要： A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
摘要翻译： 并行执行前导线程和后退线程。 假设每个部分没有发生瞬态故障，则在该部分中推测性地执行一个系统，其中前导线和尾线最好分配给两个不同的核。 此时，同时执行前导线程和后退线程，对线程本地区域执行缓冲操作，而不对共享存储器执行写入操作。 当两个线程的相应执行结果相互匹配时，缓存到线程局部区域的内容被提交并写入共享存储器。 当两个线程的相应执行结果彼此不匹配时，前导线程和后退线程将回滚到先前的提交点并重新执行。
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