公开(公告)号：US09870042B2

公开(公告)日：2018-01-16

申请号：US14275311

申请日：2014-05-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Min Young Son ,  Seung Won Lee ,  Shi Hwa Lee ,  Jae Don Lee ,  Chae Seok Im ,  Min Kyu Jeong

IPC分类号： G06F1/32 ,  G06F9/45

CPC分类号： G06F1/3234 ,  G06F1/3243 ,  G06F1/329 ,  G06F8/4432 ,  Y02B70/16 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D10/41

摘要： A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.

公开(公告)号：US09690360B2

公开(公告)日：2017-06-27

申请号：US14998273

申请日：2015-12-26

申请人： Intel Corporation

发明人： Sara S. Baghsorkhi

IPC分类号： G06F11/00 ,  G06F1/32 ,  G06F9/45 ,  G06F11/14

CPC分类号： G06F1/329 ,  G06F8/4432 ,  G06F9/50 ,  G06F11/1441 ,  G06F11/1474 ,  G06F11/3013 ,  G06F11/3062 ,  G06F2201/805 ,  G06F2201/85 ,  G06F2201/87 ,  Y02D10/41

摘要： Technologies for discontinuous execution include a compiler computing device and one or more target computing devices. The compiler computing device converts a computer program into a sequence of atomic transactions and coalesces the transactions to generate additional sequences of transactions. The compiler computing device generates an executable program including two or more sequences of transactions having different granularity. A target computing device selects an active sequence of transactions from the executable program based on the granularity of the sequence and a confidence level. The confidence level is indicative of available energy produced by an energy harvesting unit of the target computing device. The target computing device increases the confidence level in response to successfully committing transactions from the active sequence of transactions into non-volatile memory. In response to a power failure, the target computing device resets the confidence level and resumes executing the transactions. Other embodiments are described and claimed.

公开(公告)号：US20170045927A1

公开(公告)日：2017-02-16

申请号：US14998273

申请日：2015-12-26

申请人： Sara S. Bahgsorkhi

发明人： Sara S. Bahgsorkhi

IPC分类号： G06F1/32 ,  G06F11/14 ,  G06F9/45

CPC分类号： G06F1/329 ,  G06F8/4432 ,  G06F9/50 ,  G06F11/1441 ,  G06F11/1474 ,  G06F11/3013 ,  G06F11/3062 ,  G06F2201/805 ,  G06F2201/85 ,  G06F2201/87 ,  Y02D10/41

摘要： Technologies for discontinuous execution include a compiler computing device and one or more target computing devices. The compiler computing device converts a computer program into a sequence of atomic transactions and coalesces the transactions to generate additional sequences of transactions. The compiler computing device generates an executable program including two or more sequences of transactions having different granularity. A target computing device selects an active sequence of transactions from the executable program based on the granularity of the sequence and a confidence level. The confidence level is indicative of available energy produced by an energy harvesting unit of the target computing device. The target computing device increases the confidence level in response to successfully committing transactions from the active sequence of transactions into non-volatile memory. In response to a power failure, the target computing device resets the confidence level and resumes executing the transactions. Other embodiments are described and claimed.

摘要翻译： 用于不连续执行的技术包括编译器计算设备和一个或多个目标计算设备。 编译器计算设备将计算机程序转换成原子事务序列，并且合并事务以产生附加的事务序列。 编译器计算设备生成包括具有不同粒度的两个或更多个事务序列的可执行程序。 目标计算设备基于序列的粒度和置信水平从可执行程序中选择活动的事务序列。 置信水平指示由目标计算设备的能量收集单元产生的可用能量。 目标计算设备响应于成功地将事务从主动事务序列提交到非易失性存储器而增加置信水平。 响应于电源故障，目标计算设备重置置信水平并恢复执行事务。 描述和要求保护其他实施例。

公开(公告)号：US20150301583A1

公开(公告)日：2015-10-22

申请号：US14752787

申请日：2015-06-26

申请人： Empire Technology Development LLC

发明人： Miodrag Potkonjak

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F8/4432 ,  Y02D10/41

摘要： Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.

摘要翻译： 这里通常描述技术来支持用于硬件定制和能量优化的程序和数据注释。 可以检查要注释的代码块，并且可以确定硬件定制以支持具有降低的能量消耗来执行代码块的指定服务质量水平。可以将确定的确定与所确定的硬件定制相关联。 可以提供注释来指示在执行代码块时使用硬件定制。 检查代码块可以包括执行符号分析，执行代码块的执行的经验观察，执行统计分析或其任何组合中的一个或多个。 还可以检查要注释的数据块。 可以确定与数据块相关联的一个或多个附加注释。

公开(公告)号：US20150026671A1

公开(公告)日：2015-01-22

申请号：US14129956

申请日：2013-03-27

申请人： Marc Lupon ,  Raul Martinez ,  Enric Gibert Codina ,  Kyriakos A. Stavrou ,  Grigorios Magklis ,  Sridhar Samudrala

发明人： Marc Lupon ,  Raul Martinez ,  Enric Gibert Codina ,  Kyriakos A. Stavrou ,  Grigorios Magklis ,  Sridhar Samudrala

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/4432 ,  G06F8/4434 ,  G06F8/4441 ,  Y02D10/41

摘要： A mechanism is described for facilitating dynamic and efficient fusion of computing instructions according to one embodiment. A method of embodiments, as described herein, includes monitoring a software program for a program region having fusion candidate instructions for a fusion operation at a computing system; evaluating whether the macro operation of the candidate instructions is valuable to the software program; and performing the fusion operation if it is evaluated to be valuable.

摘要翻译： 描述了根据一个实施例的用于促进计算指令的动态和有效融合的机制。 如本文所述的实施例的方法包括监视具有用于在计算系统处的融合操作的融合候选指令的程序区域的软件程序; 评估候选指令的宏操作是否对软件程序有价值; 如果评估为有价值，则进行融合操作。

公开(公告)号：US20140372994A1

公开(公告)日：2014-12-18

申请号：US14212737

申请日：2014-03-14

申请人： BlueRISC Inc.

发明人： Saurabh Chheda ,  Kristopher Carver ,  Raksit Ashok

IPC分类号： G06F9/45

CPC分类号： G06F8/4432 ,  G06F9/30083 ,  Y02D10/41

摘要： A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

摘要翻译： 一种方法，包括在编译时对可执行程序进行分析和变换，从而优化处理器设计目标。 一种方法，包括分析可执行程序以估计处理器中的应用组件的能量消耗。 一种方法，包括转换可执行文件以减少处理器中的能量消耗。 由编译器插入的控制控制的处理器框架，其在指令序列中静态地暴露并行性。 一种处理器框架，用于通过编译器插入控制来减少指令存储系统中的能耗。

公开(公告)号：US08726281B2

公开(公告)日：2014-05-13

申请号：US12869610

申请日：2010-08-26

申请人： Praveen Raghavan ,  David Novo Bruna ,  Francky Catthoor ,  Angeliki Krithikakou

发明人： Praveen Raghavan ,  David Novo Bruna ,  Francky Catthoor ,  Angeliki Krithikakou

IPC分类号： G06F9/46

CPC分类号： G06F8/4432 ,  G06F8/4441 ,  Y02D10/41

摘要： A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations.

摘要翻译： 公开了一种用于将第一程序代码转换为第二程序代码的方法和装置，使得第二程序代码在目标可编程平台上具有改进的执行。 一方面，该方法包括对目标平台的功能单元上的联合执行的数据进行分组操作，及时对数据进行调度操作，以及将操作分配给目标平台的适当的功能单元。 详细的字长信息，而不是象二次幂的一般使用的近似，可以用于分组，调度或分配操作中的至少一个。

公开(公告)号：US20140115569A1

公开(公告)日：2014-04-24

申请号：US13658723

申请日：2012-10-23

申请人： Yong-Kyu Jung

发明人： Yong-Kyu Jung

IPC分类号： G06F9/45

CPC分类号： G06F8/4432 ,  G06F8/4442 ,  Y02D10/41

摘要： A method and system of the instruction packing and scaling are designed for simultaneously enhancing energy efficiency by concurrent and advanced prefetching/fetching instructions via the small and/or banked caches and for improving the performance of microprocessors by reducing the fraction of program and by employing the simple and fast caches. The invention is also designed for converting high fraction code to simplified, branch-reduced, and hidden code during compilation time, for storing packed/scaled code to concurrently accessible the plurality of caches and main memories, and for reverting the code to the native instructions during the instruction prefetch and fetch operations. Consequently, the invention does not forward many flow control instructions including procedure callers/returns and unconditional branches to microprocessors. In particular, the invention accurately prefetches/fetches instructions from the main memories to small, simple, and fast caches, which significantly reduce leakage and dynamic power dissipation, access time, and chip area.

摘要翻译： 指令包装和缩放的方法和系统被设计成通过并行和高级预取/提取指令通过小和/或银行的高速缓存同时提高能量效率，并且通过减少程序的分数并通过采用方法来提高微处理器的性能 简单快捷的缓存。 本发明还被设计用于在编译时间期间将高分数代码转换为简化的，分支减少的和隐藏的代码，用于将打包/缩放的代码存储以可同时访问多个高速缓存和主存储器，以及将代码恢复到本机指令 在指令预取和提取操作期间。 因此，本发明不将许多流程控制指令转发到微处理器，包括过程调用者/返回和无条件分支。 特别地，本发明将从主存储器的指令精确地预取/取出到小型，简单和快速的高速缓存，这显着地减少了泄漏和动态功耗，访问时间和芯片面积。

公开(公告)号：US08543993B2

公开(公告)日：2013-09-24

申请号：US12726526

申请日：2010-03-18

申请人： Koichiro Yamashita

发明人： Koichiro Yamashita

IPC分类号： G06F9/45

CPC分类号： G06F8/452 ,  G06F8/4432 ,  G06F9/50 ,  Y02D10/22 ,  Y02D10/41

摘要： A compiler compiling a source code and is implemented in a plurality of processor cores includes a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent parallel loop processing code in the internal processing operation performed for each repetition to be concurrently processed, and a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code.

摘要翻译： 编译源代码并实现在多个处理器核心中的编译器包括并行循环处理检测单元，其被配置为从源代码检测用于对给定次数的重复次数执行内部处理操作的循环处理代码，以及 对每个重复执行的内部处理操作中的独立并行环处理代码进行并行处理;以及动态并行转换单元，被配置为生成用于控制并行循环处理代码中的重复次数的控制核心代码和并行处理 用于从控制核心码改变对应于控制的重复次数的代码。

公开(公告)号：US20130145132A1

公开(公告)日：2013-06-06

申请号：US13669687

申请日：2012-11-06

申请人： BlueRISC Inc.

发明人： Csaba Andras Moritz

IPC分类号： G06F1/32

CPC分类号： G06F8/44 ,  G06F1/32 ,  G06F8/4432 ,  Y02D10/41

摘要： A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.