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    Compressing address communications between processors
    3.
    发明授权
    Compressing address communications between processors 有权
    压缩处理器之间的地址通信

    公开(公告)号：US07698512B2

    公开(公告)日：2010-04-13

    申请号：US11827904

    申请日：2007-07-13

    Applicant: Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

    Inventor： Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

    IPC: G06F12/00

    CPC classification number: G06F12/084 ,  G06F12/0833 ,  Y02D10/13

    Abstract: In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址 如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。 描述和要求保护其他实施例。

    Meeting point thread characterization
    4.
    发明授权
    Meeting point thread characterization 有权
    汇点线程表征

    公开(公告)号：US07665000B2

    公开(公告)日：2010-02-16

    申请号：US11714938

    申请日：2007-03-07

    Applicant: Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

    Inventor： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

    IPC: G01R31/28

    CPC classification number: G06F9/52 ,  G06F11/3404 ,  G06F11/3495

    Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

    Abstract translation: 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

    Double rounded combined floating-point multiply and add
    7.
    发明授权
    Double rounded combined floating-point multiply and add 有权
    双圆形组合浮点乘法和加法

    公开(公告)号：US09213523B2

    公开(公告)日：2015-12-15

    申请号：US13539198

    申请日：2012-06-29

    Applicant: Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/38 ,  G06F7/483 ,  G06F7/544

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    Abstract translation: 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

    Thread migration to improve power efficiency in a parallel processing environment
    8.
    发明授权
    Thread migration to improve power efficiency in a parallel processing environment 有权
    线程迁移以提高并行处理环境中的功率效率

    公开(公告)号：US08806491B2

    公开(公告)日：2014-08-12

    申请号：US13453904

    申请日：2012-04-23

    Applicant: Qiong Cai ,  José González ,  Pedro Chappero Monferrer ,  Grigorios Magklis ,  Antonio González

    Inventor： Qiong Cai ,  José González ,  Pedro Chappero Monferrer ,  Grigorios Magklis ,  Antonio González

    IPC: G06F9/46 ,  G06F1/00

    CPC classification number: G06F9/5094 ,  G06F1/329 ,  Y02D10/22 ,  Y02D10/24

    Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

    Abstract translation: 一种选择性地移动由多个处理核并行执行的多个线程中的一个或多个的方法和系统。 在一个实施例中，可以将线程从执行多个处理核心中的一个移动到在多个处理核心中的另一个处理核心中执行，基于与多个线程相关联的性能特性来移动线程。 在本发明的另一实施例中，可以改变多个处理核心的功率状态，以提高与执行多个线程相关联的功率效率。

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