公开(公告)号：US20070157206A1

公开(公告)日：2007-07-05

申请号：US11322823

申请日：2005-12-30

Applicant: Ryan Rakvic ,  Richard Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

Inventor： Ryan Rakvic ,  Richard Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

IPC: G06F9/46

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract translation: 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。

公开(公告)号：US20070124732A1

公开(公告)日：2007-05-31

申请号：US11289803

申请日：2005-11-29

Applicant: Shih-wei Lia ,  Ryan Rakvic ,  Richard Hankins ,  Hong Wang ,  Gansha Wu ,  Guei-Yuan Lueh ,  Xinmin Tian ,  Paul Petersen ,  Sanjiv Shah ,  Trung Diep ,  John Shen ,  Gautham Chinya

Inventor： Shih-wei Lia ,  Ryan Rakvic ,  Richard Hankins ,  Hong Wang ,  Gansha Wu ,  Guei-Yuan Lueh ,  Xinmin Tian ,  Paul Petersen ,  Sanjiv Shah ,  Trung Diep ,  John Shen ,  Gautham Chinya

IPC: G06F9/46

CPC classification number: G06F9/485 ,  G06F9/4881

Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例来调度用户级别的与OS无关的“碎片”，而不需要操作系统的干预。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以从编译器接收编译器生成的提示。 编译器提示可能由编译器生成，而不需要用户提供的编译指示，并且可以通过类API接口传递给调度程序。 接口可以包括由编译器维护的调度提示数据结构。 还描述和要求保护其他实施例。

公开(公告)号：US08839258B2

公开(公告)日：2014-09-16

申请号：US13354623

申请日：2012-01-20

Applicant: Ryan Rakvic ,  Richard A. Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David K. Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

Inventor： Ryan Rakvic ,  Richard A. Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David K. Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

IPC: G06F9/46 ,  G06F1/00 ,  G06F1/26 ,  G06F9/48

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract translation: 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。

公开(公告)号：US20120131366A1

公开(公告)日：2012-05-24

申请号：US13354623

申请日：2012-01-20

Applicant: Ryan Rakvic ,  Richard A. Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David K. Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

Inventor： Ryan Rakvic ,  Richard A. Hankins ,  Ed Grochowski ,  Hong Wang ,  Murali Annavaram ,  David K. Poulsen ,  Sanjiv Shah ,  John Shen ,  Gautham Chinya

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F9/4893 ,  Y02D10/24

Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Abstract translation: 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。

公开(公告)号：US20080222466A1

公开(公告)日：2008-09-11

申请号：US11714938

申请日：2007-03-07

Applicant: Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

Inventor： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

IPC: G01R31/28

CPC classification number: G06F9/52 ,  G06F11/3404 ,  G06F11/3495

Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

Abstract translation: 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，临界点可以通过检查会议点数来确定。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

公开(公告)号：US07665000B2

公开(公告)日：2010-02-16

申请号：US11714938

申请日：2007-03-07

Applicant: Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

Inventor： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

IPC: G01R31/28

CPC classification number: G06F9/52 ,  G06F11/3404 ,  G06F11/3495

Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

Abstract translation: 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

公开(公告)号：US07120749B2

公开(公告)日：2006-10-10

申请号：US10803452

申请日：2004-03-18

Applicant: Ryan Rakvic ,  Youfeng Wu ,  Bryan Black ,  John Shen

Inventor： Ryan Rakvic ,  Youfeng Wu ,  Bryan Black ,  John Shen

IPC: G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/0888

Abstract: According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.

Abstract translation: 根据一个实施例，公开了一种系统。 该系统包括中央处理单元（CPU），第一高速缓存存储器，其耦合到CPU以仅存储要在CPU处理的重要负载的数据;耦合到CPU的第二高速缓存存储器， 在CPU处理的重要负载，以及耦合到CPU，第一高速缓冲存储器和第二高速缓冲存储器的第三高速缓存存储器，用于存储要在CPU处理的非重要负载。

公开(公告)号：US20060224858A1

公开(公告)日：2006-10-05

申请号：US11100032

申请日：2005-04-05

Applicant: Hong Wang ,  Gautham Chinya ,  Richard Hankins ,  Shivnandan Kaushik ,  Bryant Bigbee ,  Per Hammarlund ,  Xiang Zou ,  Jason Brandt ,  Prashant Sethi ,  Douglas Carmean ,  Baiju Patel ,  John Shen ,  Scott Rodgers ,  Ryan Rakvic ,  John Reid ,  David Poulsen ,  Sanjiv Shah ,  James Held ,  James Abel

Inventor： Hong Wang ,  Gautham Chinya ,  Richard Hankins ,  Shivnandan Kaushik ,  Bryant Bigbee ,  Per Hammarlund ,  Xiang Zou ,  Jason Brandt ,  Prashant Sethi ,  Douglas Carmean ,  Baiju Patel ,  John Shen ,  Scott Rodgers ,  Ryan Rakvic ,  John Reid ,  David Poulsen ,  Sanjiv Shah ,  James Held ,  James Abel

IPC: G06F12/00

CPC classification number: G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract translation: 公开了用于管理和转换逻辑定序器地址与多序列器多线程系统中的物理或逻辑顺控程序之间的映射的系统，方法和机制的实施例。 映射管理器可以管理逻辑顺控程序地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这样的映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US20060117141A1

公开(公告)日：2006-06-01

申请号：US11327454

申请日：2006-01-09

Applicant: Ryan Rakvic ,  John Shen ,  Deepak Limaye

Inventor： Ryan Rakvic ,  John Shen ,  Deepak Limaye

IPC: G06F13/00

CPC classification number: G06F12/0864 ,  G06F12/0897

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

公开(公告)号：US06954848B2

公开(公告)日：2005-10-11

申请号：US10038038

申请日：2002-01-02

Applicant: Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

Inventor： Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Abstract translation: 在第一次指令将数据加载到寄存器中之后，监视寄存器以查看是否在下一个时钟周期读取。 当数据在下一个时钟周期内未被读取时，指令被分类为慢指令。 与指令相关联的指令地址用于更新历史表。 历史表存储用于指示指令是指令是慢指令还是非慢指令的信息。 当第二次遇到指令的指令地址时，使用历史表来确定指令是可慢还是不慢。