Methods and apparatuses for addressing memory caches
    7.
    发明授权
    Methods and apparatuses for addressing memory caches 有权
    寻址内存缓存的方法和设备

    公开(公告)号:US09569359B2

    公开(公告)日:2017-02-14

    申请号:US14001464

    申请日:2012-02-22

    IPC分类号: G06F12/00 G06F12/08 G11C7/10

    摘要: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

    摘要翻译: 缓存存储器包括用于存储信息的高速缓存行。 存储的信息与包括第一,第二和第三不同部分的物理地址相关联。 高速缓存线由与存储的信息相关联的相应物理地址的第二部分索引。 高速缓冲存储器还包括一个或多个表,每个表包括由相应物理地址的第一部分索引的各个表条目。 一个或多个表中的每一个中的相应表条目是存储与存储的信息相关联的相应物理地址的第二部分的指示。