公开(公告)号：US20130219096A1

公开(公告)日：2013-08-22

申请号：US13844343

申请日：2013-03-15

Applicant: HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

Inventor： HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract translation: 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US08719839B2

公开(公告)日：2014-05-06

申请号：US13504972

申请日：2009-10-30

Applicant: Shoumeng Yan ,  Xiaocheng Zhou ,  Ying Gao ,  Mohan Rajagopalan ,  Rajiv Deodhar ,  David Putzolu ,  Clark Nelson ,  Milind Girkar ,  Robert Geva ,  Tiger Chen ,  Sai Luo ,  Stephen Junkins ,  Bratin Saha ,  Ravi Narayanaswamy ,  Patrick Xi

Inventor： Shoumeng Yan ,  Xiaocheng Zhou ,  Ying Gao ,  Mohan Rajagopalan ,  Rajiv Deodhar ,  David Putzolu ,  Clark Nelson ,  Milind Girkar ,  Robert Geva ,  Tiger Chen ,  Sai Luo ,  Stephen Junkins ,  Bratin Saha ,  Ravi Narayanaswamy ,  Patrick Xi

IPC: G06F9/44 ,  G06F9/45 ,  G06F15/00

CPC classification number: G06F9/544 ,  G06F9/547

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU, for example. The GPU may be coupled to a GPU compiler and a GPU linker/loader and the CPU may be coupled to a CPU compiler and a CPU linker/loader. The user may create a shared object in an object oriented language and the shared object may include virtual functions. The shared object may be fine grain partitioned between the heterogeneous processors. The GPU compiler may allocate the shared object to the CPU and may create a first and a second enabling path to allow the GPU to invoke virtual functions of the shared object. Thus, the shared object that may include virtual functions may be shared seamlessly between the CPU and the GPU.

Abstract translation: 计算机系统可以包括计算机平台和输入 - 输出设备。 计算机平台可以包括例如包括中央处理单元（CPU）和图形处理单元（GPU）的多个异构处理器。 GPU可以耦合到GPU编译器和GPU链接器/加载器，并且CPU可以耦合到CPU编译器和CPU链接器/加载器。 用户可以以面向对象的语言创建共享对象，并且共享对象可以包括虚拟功能。 共享对象可以是异构处理器之间的细粒度分区。 GPU编译器可以将共享对象分配给CPU，并且可以创建第一和第二启用路径以允许GPU调用共享对象的虚拟功能。 因此，可以包括虚拟功能的共享对象可以在CPU和GPU之间无缝共享。

公开(公告)号：US07571301B2

公开(公告)日：2009-08-04

申请号：US11395841

申请日：2006-03-31

Applicant: Arun Kejariwal ,  Hideki Saito ,  Xinmin Tian ,  Milind Girkar ,  Sanjiv Shah ,  Wei Li ,  Utpal Banerjee

Inventor： Arun Kejariwal ,  Hideki Saito ,  Xinmin Tian ,  Milind Girkar ,  Sanjiv Shah ,  Wei Li ,  Utpal Banerjee

IPC: G06F9/45 ,  G06F9/52

CPC classification number: G06F9/3009 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3891

Abstract: A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.

Abstract translation: 一种改进计算机程序并行处理的方法。 DOACROSS循环和类似代码使用后等待控制结构进行标识和并行化。 后等待控制结构可以被实现为包括执行执行顺序的单个计数器中的任何一个，用于跟踪由正整数的模数索引的代码完成的数组，和/或一组数组 跟踪由线程完成的最后一个代码以及由线程执行的当前代码。

公开(公告)号：US07398521B2

公开(公告)日：2008-07-08

申请号：US10779193

申请日：2004-02-13

Applicant: Gerolf F. Hoflehner ,  Shih-wei Liao ,  Xinmin Tian ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

Inventor： Gerolf F. Hoflehner ,  Shih-wei Liao ,  Xinmin Tian ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Abstract translation: 本文描述了用于多线程的线程管理的方法和装置。 在一个实施例中，示例性过程包括在具有在数据处理系统中可执行的一个或多个线程的代码的编译期间选择具有最低阶的当前线程，确定分配给从当前线程产生的一个或多个子线程的资源， 并且考虑分配给当前线程的一个或多个子线程的资源来为当前线程分配资源，以避免当前线程与其一个或多个子线程之间的资源冲突。 还描述了其它方法和装置。

公开(公告)号：US20070234326A1

公开(公告)日：2007-10-04

申请号：US11395841

申请日：2006-03-31

Applicant: Arun Kejariwal ,  Hideki Saito ,  Xinmin Tian ,  Milind Girkar ,  Sanjiv Shah ,  Wei Li ,  Utpal Banerjee

Inventor： Arun Kejariwal ,  Hideki Saito ,  Xinmin Tian ,  Milind Girkar ,  Sanjiv Shah ,  Wei Li ,  Utpal Banerjee

IPC: G06F9/45

CPC classification number: G06F9/3009 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3891

Abstract: A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.

Abstract translation: 一种改进计算机程序并行处理的方法。 DOACROSS循环和类似代码使用后等待控制结构进行标识和并行化。 后等待控制结构可以被实现为包括执行执行顺序的单个计数器中的任何一个，用于跟踪由正整数的模数索引的代码完成的数组，和/或一组数组 跟踪由线程完成的最后一个代码以及由线程执行的当前代码。

公开(公告)号：US20050071438A1

公开(公告)日：2005-03-31

申请号：US10676889

申请日：2003-09-30

Applicant: Shih-Wei Liao ,  Xinmin Tian ,  Gerolf Hoflehner ,  Hong Wang ,  Daniel Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John Shen

Inventor： Shih-Wei Liao ,  Xinmin Tian ,  Gerolf Hoflehner ,  Hong Wang ,  Daniel Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John Shen

IPC: G06F9/38 ,  G06F9/45 ,  G06F15/167

CPC classification number: G06F9/3842 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/3851

Abstract: Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Abstract translation: 本文描述了用于多线程的编译器创建的辅助线程的方法和装置。 在一个实施例中，示例性过程包括识别可能具有一个或多个拖欠负载的主线程的区域，所述一个或多个违规负载表示在执行主线程期间可能遭受高速缓存未命中的负载，分析该区域中的一个或多个 相对于主线程的更多帮助线程，以及为一个或多个辅助线程生成代码，一个或多个辅助线程与主线程并行地被推测地执行，以对主线程的区域执行一个或多个任务。 还描述了其它方法和装置。

公开(公告)号：US20180060258A1

公开(公告)日：2018-03-01

申请号：US15804939

申请日：2017-11-06

Applicant: HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

Inventor： HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

IPC: G06F13/24 ,  G06F9/30 ,  G06F11/34 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US08612949B2

公开(公告)日：2013-12-17

申请号：US12650630

申请日：2009-12-31

Applicant: Shih-wei Liao ,  Xinmin Tian ,  Gerolf F. Hoflehner ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

Inventor： Shih-wei Liao ,  Xinmin Tian ,  Gerolf F. Hoflehner ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

IPC: G06F9/45

CPC classification number: G06F9/3842 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/3851

Abstract: Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Abstract translation: 本文描述了用于多线程的编译器创建的辅助线程的方法和装置。 在一个实施例中，示例性过程包括识别可能具有一个或多个拖欠负载的主线程的区域，所述一个或多个违规负载表示在执行主线程期间可能遭受高速缓存未命中的负载，分析该区域中的一个或多个 相对于主线程的更多帮助线程，以及为一个或多个辅助线程生成代码，一个或多个辅助线程与主线程并行地被推测地执行，以对主线程的区域执行一个或多个任务。 还描述了其它方法和装置。

公开(公告)号：US08037465B2

公开(公告)日：2011-10-11

申请号：US11242489

申请日：2005-09-30

Applicant: Xinmin Tian ,  Milind Girkar ,  David C. Sehr ,  Richard Grove ,  Wei Li ,  Hong Wang ,  Chris Newburn ,  Perry Wang ,  John Shen

Inventor： Xinmin Tian ,  Milind Girkar ,  David C. Sehr ,  Richard Grove ,  Wei Li ,  Hong Wang ,  Chris Newburn ,  Perry Wang ,  John Shen

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/45

Abstract: Thread-data affinity optimization can be performed by a compiler during the compiling of a computer program to be executed on a cache coherent non-uniform memory access (cc-NUMA) platform. In one embodiment, the present invention includes receiving a program to be compiled. The received program is then compiled in a first pass and executed. During execution, the compiler collects profiling data using a profiling tool. Then, in a second pass, the compiler performs thread-data affinity optimization on the program using the collected profiling data.

Abstract translation: 线程数据亲和度优化可以在编译要在高速缓存相干非均匀内存访问（cc-NUMA）平台上执行的计算机程序时由编译器执行。 在一个实施例中，本发明包括接收要编译的程序。 接收的程序然后被编译成第一遍并被执行。 在执行期间，编译器使用分析工具收集分析数据。 然后，在第二遍，编译器使用收集的分析数据对程序执行线程数据关联优化。

公开(公告)号：US20100281471A1

公开(公告)日：2010-11-04

申请号：US12650630

申请日：2009-12-31

Applicant: Shih-Wei Liao ,  Xinmin Tian ,  Gerolf F. Hoflehner ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

Inventor： Shih-Wei Liao ,  Xinmin Tian ,  Gerolf F. Hoflehner ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

IPC: G06F9/45 ,  G06F9/46

CPC classification number: G06F9/3842 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/3851

Abstract: Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Abstract translation: 本文描述了用于多线程的编译器创建的辅助线程的方法和装置。 在一个实施例中，示例性过程包括识别可能具有一个或多个拖欠负载的主线程的区域，所述一个或多个违规负载表示在执行主线程期间可能遭受高速缓存未命中的负载，分析该区域中的一个或多个 相对于主线程的更多帮助线程，以及为一个或多个辅助线程生成代码，一个或多个辅助线程与主线程并行地被推测地执行，以对主线程的区域执行一个或多个任务。 还描述了其它方法和装置。