公开(公告)号：US08125246B2

公开(公告)日：2012-02-28

申请号：US12618629

申请日：2009-11-13

Applicant: Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

Inventor： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

IPC: H03K19/096

CPC classification number: G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract translation: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US20100052730A1

公开(公告)日：2010-03-04

申请号：US12618629

申请日：2009-11-13

Applicant: Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

Inventor： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

IPC: H03K5/19

CPC classification number: G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract translation: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US07480838B1

公开(公告)日：2009-01-20

申请号：US11388668

申请日：2006-03-23

Applicant: Chris Wilkerson ,  Shih-Lien L. Lu ,  Edward Grochowski ,  Murali Annavaram

Inventor： Chris Wilkerson ,  Shih-Lien L. Lu ,  Edward Grochowski ,  Murali Annavaram

IPC: G06K5/04

CPC classification number: G06F11/0751 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/1497

Abstract: Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.

Abstract translation: 包括用于报告从电路电平到功能单元块（FUB）到全局检测的定时误差检测的层次结构的集成设备的检测内部定时误差的有效电路的方法和系统以及重新排序 缓冲器（ROB），用于存储用于定时错误恢复的结果，直到定时可被验证为无错误。

公开(公告)号：US20050188185A1

公开(公告)日：2005-08-25

申请号：US10783765

申请日：2004-02-20

Applicant: Edward Grochowski

Inventor： Edward Grochowski

IPC: G06F9/00 ,  G06F9/318

CPC classification number: G06F9/30072 ,  G06F9/30145

Abstract: A method and apparatus for implementing predicated instructions using selective conversion to micro-operations is presented. In one embodiment, the predicated instructions may have both a prediction of the predicate value and an indication of the confidence value of that predicted predicate value generated. When the confidence value of the prediction is low, then the predicated instruction may be decomposed into a set of micro-operations that should execute whether the predicate value is true or false. But when the confidence value is high, then the predicated instruction may be decomposed into simpler sets of micro-operations, for the cases when the predicted predicate value is true and for when it is false.

Abstract translation: 提出了一种使用选择性转换为微操作来实现预测指令的方法和装置。 在一个实施例中，所述预测指令可以具有所述谓词值的预测和所生成的所述预测谓词值的置信度值的指示。 当预测的置信度值低时，则可以将预测指令分解为应该执行谓词值是真还是假的一组微操作。 但是，当置信度值高时，对于预测的谓词值为真，以及当为假时，预测指令可能被分解成更简单的微操作集合。

公开(公告)号：US20050138340A1

公开(公告)日：2005-06-23

申请号：US10744186

申请日：2003-12-22

Applicant: Yong-Fong Lee ,  Partha Kundu ,  Edward Grochowski

Inventor： Yong-Fong Lee ,  Partha Kundu ,  Edward Grochowski

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/40

CPC classification number: G06F9/30105 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/4484

Abstract: A method and apparatus for selectively storing a register stack onto a register stack backing store is disclosed. In one embodiment, a non-exclusive boundary is determined enclosing registers that were actually used (e.g. written to) by a function. The description of that boundary is saved, and only the contents of the registers within the boundary are saved to register stack backing store as part of a spill operation. When the function is later restored, the description of the boundary is recalled and used to support the loading of just those registers from the register stack backing store as part of a fill operation.

Abstract translation: 公开了一种用于将寄存器堆栈选择性地存储到寄存器堆栈后备存储器上的方法和装置。 在一个实施例中，确定包围实际使用（例如写入）功能的寄存器的非排他边界。 保存该边界的描述，只有边界内的寄存器的内容才能保存到寄存器堆栈后备存储中，作为溢出操作的一部分。 当函数稍后恢复时，边界的描述被调用并用于支持从寄存器堆栈后备存储器中仅加载这些寄存器作为填充操作的一部分。

公开(公告)号：US06826588B2

公开(公告)日：2004-11-30

申请号：US10032026

申请日：2001-12-17

Applicant: Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

Inventor： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC: G06F702

CPC classification number: G06F7/48 ,  G06F7/02 ,  G06F7/026 ,  G06F7/4824

Abstract: The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

Abstract translation: 本发明提供了一种用于以冗余形式旁路输出到算术电路的有效方法，该算术电路能够从冗余形式中增加或减少冗余中的数字并比较用于相等和不等式关系的以冗余形式接收的数字的数量。 对于本发明的一个实施例，运算电路减去以冗余形式接收的数字，并将结果与​​以多余形式表示的零进行比较，而无需进位传播。 与减法和比较并行地，以冗余形式接收的每个数字的最高有效位被生成和比较以相等，并且为减法产生进位输出。 这些结果通过幅度比较逻辑组合，以产生以冗余形式接收的数字的幅度比较。

公开(公告)号：US06763368B2

公开(公告)日：2004-07-13

申请号：US09746940

申请日：2000-12-22

Applicant: Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

Inventor： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC: G06F704

CPC classification number: G06F7/5095 ,  G06F7/02 ,  G06F7/4824

Abstract: A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operation on operands received in redundant form to generate a result represented in redundant form. A comparator circuit is coupled with the arithmetic circuit to receive the result in redundant form and to perform an equality comparison of the result to the expected value, and to indicate the truth of said equality comparison independent of carry signal propagation from the least significant digit to the most significant digit.

Abstract translation: 一种用于添加以冗余形式表示的数字或用于减去以冗余形式接收的数字并用于将用于相等的冗余形式的结果与期望值进行比较的方法和装置。 冗余算术电路对以冗余形式接收的操作数执行算术运算，以生成以冗余形式表示的结果。 比较器电路与算术电路耦合以以冗余形式接收结果，并且执行结果与期望值的相等比较，并且指示所述等式比较的真实性，独立于从最低有效数字到进位信号传播的进位信号 最重要的数字。

公开(公告)号：US5581718A

公开(公告)日：1996-12-03

申请号：US276089

申请日：1994-07-15

Applicant: Edward Grochowski

Inventor： Edward Grochowski

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F13/00

CPC classification number: G06F9/3816 ,  G06F9/30149

Abstract: A method and apparatus for selecting instructions from a sequence of undifferentiated bytes of instruction data is described. A first plurality of sequential bytes of instruction data is selected from the sequence of undifferentiated bytes of instruction data. A second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality is selected from the first plurality of sequential bytes of instruction data. A third plurality of sequential bytes of instruction data beginning at any selected byte in the second plurality is selected from the second plurality of sequential bytes of instruction data. The second plurality of sequential bytes is of sufficient length to provide instruction data for at least two clock cycles.

Abstract translation: 描述了用于从指令数据的未分化字节序列中选择指令的方法和装置。 从指令数据的未分化字节的序列中选择指令数据的第一多个顺序字节。 从指令数据的第一多个顺序字节中选择从第一多个中的任何选定字节开始的指令数据的第二多个连续字节。 从指令数据的第二多个顺序字节中选择从第二多个中的任何选定字节开始的第三组连续字节的指令数据。 第二多个顺序字节具有足够的长度以提供至少两个时钟周期的指令数据。

公开(公告)号：US5450605A

公开(公告)日：1995-09-12

申请号：US10360

申请日：1993-01-28

Applicant: Edward Grochowski ,  Kenneth Shoemaker ,  Uri Weiser ,  Doron Orenstein

Inventor： Edward Grochowski ,  Kenneth Shoemaker ,  Uri Weiser ,  Doron Orenstein

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F12/04 ,  G06F13/16

CPC classification number: G06F9/30152 ,  G06F9/3816 ,  G06F9/3885

Abstract: The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.

Abstract translation: 本说明书公开了一种用于确定在不区分的指令流中顺序出现的可变长度指令的长度的方法和装置。 该装置可以用于促进计算机系统对这种可变长度指令的并行处理。 该装置包括：用于为每个指令提供边界标记以指示该指令与指令流中的另一指令之间的边界的电路，用于依次处理指令的电路，用于确定第一指令的实际边界的电路 处理的电路，用于比较第一指令的边界标记和实际边界以确定它们是否匹配的电路，用于当边界值和实际值与第一指令的边界标记更新为第一指令的实际边界的电路 第一指令的边界不匹配，以及用于基于第一指令的边界标记指示来自指令流的第一指令和下一指令之间的边界的电路。

公开(公告)号：US20070164787A1

公开(公告)日：2007-07-19

申请号：US11234548

申请日：2005-09-23

Applicant: Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

Inventor： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

IPC: H03K19/173 ,  G06F7/38

CPC classification number: G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract translation: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。