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US08125246B2 Method and apparatus for late timing transition detection 有权
用于后期定时转换检测的方法和装置

Method and apparatus for late timing transition detection
Abstract:
Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
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