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公开(公告)号：US20220100377A1
公开(公告)日：2022-03-31
申请号：US17643034
申请日：2021-12-07
发明人： Hiroshi YAO , Shinichi KANNO , Kazuhiro FUKUTOMI
摘要： According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
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公开(公告)号：US20210175907A1
公开(公告)日：2021-06-10
申请号：US17178604
申请日：2021-02-18
发明人： Riki SUZUKI , Toshikatsu HIDA , Osamu TORII , Hiroshi YAO , Kiyotaka IWASAKI
摘要： According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
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公开(公告)号：US20180356984A1
公开(公告)日：2018-12-13
申请号：US16044257
申请日：2018-07-24
发明人： Hiroshi YAO , Shinichi KANNO , Kazuhiro FUKUTOMI
CPC分类号： G06F3/0604 , G06F3/0634 , G06F3/0641 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2212/1016 , G06F2212/1024 , G06F2212/1044 , G06F2212/214 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry. The processing circuitry performs acquiring the one or more second storage areas from the plurality of first storage areas, selecting a plurality of storage areas from the plurality of third storage areas or from the plurality of fourth storage areas based on a rate of valid date in fifth storage area, the fifth storage area being the plurality of fourth storage areas, the rate of valid data in the fifth storage area being a rate of the total amount of valid data stored in the fifth storage area with respect to the total capacity of the fifth storage area, and writing the valid data stored in the selected plurality of storage areas in the acquired one or more second storage areas using the second mode.
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4.发明申请公开(公告)号：US20180039523A1
公开(公告)日：2018-02-08
申请号：US15438683
申请日：2017-02-21
发明人： Takayuki AKAMINE , Kenichiro YOSHII , Hiroshi YAO
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F2209/501
摘要： An information processing system includes a first core, a second core having a processing speed that is slower than the first core, a first memory, a second memory having a slower response time than the first memory, and a management processor. The management processor is configured to determine a core for executing a task, cause program data for executing the task to be copied to the first memory and then cause the first core to execute the task using the program data in the first memory, when the first core is determined as the core for executing the task, and cause the program data for executing the task to be copied to the second memory and then cause the second core to execute the task using the program data in the second memory, when the second core is determined as the core for executing the task.
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公开(公告)号：US20180277204A1
公开(公告)日：2018-09-27
申请号：US15703070
申请日：2017-09-13
发明人： Marie TAKADA , Masanobu SHIRAKAWA , Hiroshi YAO
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/1006 , G11C13/0026 , G11C13/0033 , G11C13/0069 , G11C2013/0042 , G11C2013/005 , G11C2013/0054 , G11C2013/0057 , G11C2213/71 , G11C2213/78 , G11C2213/79
摘要： A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. The first voltage is different from the second voltage. The first read data has a first value or a second value with the first value being different from the second value. The second read data has the first value or the second value.
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公开(公告)号：US20180076833A1
公开(公告)日：2018-03-15
申请号：US15460320
申请日：2017-03-16
发明人： Takayuki AKAMINE , Kenichiro YOSHll , Hiroshi YAO
CPC分类号： H03M13/6566 , G06F3/0604 , G06F3/0659 , G06F3/0688 , G06F13/22 , G06F13/24 , H03M13/1102 , H03M13/152 , H03M13/255 , H03M13/2909
摘要： According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. The host, in a case where the first response is received, stops the polling and receives the second response based on reception of the interrupt signal.
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