公开(公告)号：US20220100377A1

公开(公告)日：2022-03-31

申请号：US17643034

申请日：2021-12-07

申请人： Toshiba Memory Corporation

发明人： Hiroshi YAO ,  Shinichi KANNO ,  Kazuhiro FUKUTOMI

IPC分类号： G06F3/06 ,  G06F12/02

摘要： According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

公开(公告)号：US20180364924A1

公开(公告)日：2018-12-20

申请号：US16112314

申请日：2018-08-24

申请人： TOSHIBA MEMORY CORPORATION

发明人： Kazuhiro FUKUTOMI ,  Shingo TANAKA

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC分类号： G06F12/0253 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

摘要： A storage system connectable to a host includes a plurality of interface units, a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units, and a controller configured to maintain an address conversion table indicating mappings between logical addresses and physical addresses of memory locations in the semiconductor memory modules. When the controller determines that a first semiconductor memory module needs to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the corresponding logical addresses to another semiconductor memory module and update the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data.

公开(公告)号：US20200379901A1

公开(公告)日：2020-12-03

申请号：US16995029

申请日：2020-08-17

申请人： Toshiba Memory Corporation

发明人： Kazuhiro FUKUTOMI ,  Kenichiro YOSHII ,  Shinichi KANNO ,  Shigehiro ASANO

IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F12/00 ,  G06F12/16

摘要： According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

公开(公告)号：US20180356984A1

公开(公告)日：2018-12-13

申请号：US16044257

申请日：2018-07-24

申请人： Toshiba Memory Corporation

发明人： Hiroshi YAO ,  Shinichi KANNO ,  Kazuhiro FUKUTOMI

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0604 ,  G06F3/0634 ,  G06F3/0641 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205

摘要： According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry. The processing circuitry performs acquiring the one or more second storage areas from the plurality of first storage areas, selecting a plurality of storage areas from the plurality of third storage areas or from the plurality of fourth storage areas based on a rate of valid date in fifth storage area, the fifth storage area being the plurality of fourth storage areas, the rate of valid data in the fifth storage area being a rate of the total amount of valid data stored in the fifth storage area with respect to the total capacity of the fifth storage area, and writing the valid data stored in the selected plurality of storage areas in the acquired one or more second storage areas using the second mode.

公开(公告)号：US20180059969A1

公开(公告)日：2018-03-01

申请号：US15442148

申请日：2017-02-24

申请人： Toshiba Memory Corporation

发明人： Kazuhiro FUKUTOMI ,  Takahiro KURITA ,  Kazunari SUMIYOSHI ,  Kazunari KAWAMURA

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0683

摘要： A storage system includes a plurality of nodes, each of the nodes including a nonvolatile storage device, and a connection unit directly connected to at least one of the nodes and having a processor. The processor is configured to store each of input or output (I/O) commands in a queue, issue each of the data I/O commands stored in the queue to one of the nodes to be accessed in accordance with the data I/O command, determine a busy node based on a status received therefrom, and selectively generate I/O commands for storage in the queue so that I/O commands targeting non-busy nodes are generated and I/O commands targeting busy nodes are not generated.