公开(公告)号：US20030168725A1

公开(公告)日：2003-09-11

申请号：US10281550

申请日：2002-10-28

Applicant: Tessera, Inc.

Inventor： Michael Warner ,  Philip Damberg ,  John B. Riley ,  David Gibson ,  Young-Gon Kim ,  Belgacem Haba ,  Vernon Solberg

IPC: H05K001/14

CPC classification number: H05K1/189 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599

Abstract: A stacked microelectronic assembly comprises a plurality of subassemblies including folded substrates and at least one microelectronic element. The subassemblies are stacked substantially vertically.

Abstract translation: 堆叠的微电子组件包括多个子组件，其包括折叠的衬底和至少一个微电子元件。 子组件基本垂直地堆叠。

公开(公告)号：US20040031972A1

公开(公告)日：2004-02-19

申请号：US10454029

申请日：2003-06-04

Applicant: Tessera, Inc.

Inventor： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

IPC: H01L031/0336

CPC classification number: H01L23/528 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/78301 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00014

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract translation: 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，通过形成焊接桥，各个单元的多分支迹线被选择性地连接，以便在连接到不同的芯片选择端子的不同单元中留下芯片的芯片选择触点，从而将这些芯片连接到不同的垂直总线 。 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。

公开(公告)号：US20040262777A1

公开(公告)日：2004-12-30

申请号：US10683097

申请日：2003-10-10

Applicant: Tessera, Inc.

Inventor： Young-Gon Kim ,  David Gibson ,  Michael Warner ,  Philip Damberg ,  Philip Osborn

IPC: H01L023/48 ,  H01L029/40 ,  H05K007/02

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract translation: 具有独立测试和修复功能的超薄系统级封装（SIP）包括：插入器，其布置在其顶表面和底表面上，多个封装的半导体芯片通过焊料凸块安装，根据Land Grid Array （LGA）格式，并且其中在SIP上不使用底部填充物。

公开(公告)号：US20020151111A1

公开(公告)日：2002-10-17

申请号：US10162957

申请日：2002-06-05

Applicant: Tessera, Inc.

Inventor： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

IPC: H01L021/60 ,  H01L023/12

CPC classification number: H01L24/86 ,  H01L23/3107 ,  H01L23/49572 ,  H01L24/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A semiconductor chip mounting component includes a support having a top surface, a bottom surface, a central portion, a peripheral portion surrounding the central portion, and a gap extending through the support structure between the top and bottom. The component includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the support structure on one side of the gap, a second end secured to the support structure on an opposite side of the gap, and a frangible section between the first and second ends. The component also includes at least one elongated bus disposed on the peripheral portion of the support structure alongside the gap, whereby each lead extends across the gap and is connected to the bus.

Abstract translation: 半导体芯片安装部件包括具有顶表面，底表面，中心部分，围绕中心部分的周边部分以及在顶部和底部之间延伸穿过支撑结构的间隙的支撑件。 所述部件包括多个导电引线，每个引线具有跨越所述间隙延伸的连接部分，所述连接部分具有在所述间隙的一侧上设置在所述支撑结构上的第一端，在所述间隙的一侧固定到所述支撑结构的第二端 间隙的相对侧，以及第一和第二端之间的易碎部分。 该部件还包括至少一个细长总线，其沿着间隙设置在支撑结构的周边部分上，由此每个引线延伸穿过间隙并连接到总线。

公开(公告)号：US20040238922A1

公开(公告)日：2004-12-02

申请号：US10872105

申请日：2004-06-18

Applicant: Tessera, Inc.

Inventor： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan Mathieu ,  Jason Sweis ,  Laurie Union ,  David Gibson

IPC: H01L023/495

CPC classification number: H01L24/86 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49861 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/361 ,  H05K3/4084 ,  H01L2924/00

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure. A semiconductor chip is disposed beneath the bottom surface of the support structure. The leads are adapted to be bonded to contacts on the semiconductor chip by breaking the frangible sections of the leads so as to disconnect the second ends of the leads from the bus and engage the leads with the contacts of the semiconductor chip.

Abstract translation: 半导体芯片安装部件包括适于接合半导体芯片的支撑结构。 支撑结构具有顶表面，底表面和延伸穿过支撑结构的间隙，用于限定支撑结构在间隙的相对侧上的第一和第二部分。 支撑结构包括在支撑结构的第二部分上沿着间隙布置的至少一个细长总线。 支撑结构包括多个导电引线，每个引线具有跨越间隙延伸的连接部分，连接部分具有设置在支撑结构的第一部分上的第一端和固定到总线的第二端。 每个引线包括设置在连接部分的第一和第二端之间的易碎部分，该易碎部分的横截面积小于连接部分的横截面面积。 间隙在支撑结构的底部表面开口。 半导体芯片设置在支撑结构的底表面下方。 引线适于通过断开引线的易碎部分而与半导体芯片上的触点接合，从而将引线的第二端与母线断开，并与半导体芯片的触点接合引线。

公开(公告)号：US20040203190A1

公开(公告)日：2004-10-14

申请号：US10834342

申请日：2004-04-28

Applicant: Tessera, Inc.

Inventor： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell

IPC: H01L021/44

CPC classification number: H01L23/528 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract translation: 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，单个单元的多分支迹线通过断开各个分支而被选择性地中断，以便将芯片的芯片选择触点留在连接到不同芯片选择端子的不同单元中，从而将这些芯片连接到不同的垂直 巴士 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。

公开(公告)号：US20040145054A1

公开(公告)日：2004-07-29

申请号：US10656534

申请日：2003-09-05

Applicant: Tessera, Inc.

Inventor： Kyong-Mo Bang ,  David Gibson ,  Young-Gon Kim ,  John B. Riley

IPC: H01L023/48 ,  H01L021/44

CPC classification number: H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.

Abstract translation: 包括底部单元半导体芯片的底部单元安装到电路板，并且诸如封装半导体芯片的一个或多个顶部元件安装到底部单元。 可以使用与将组件安装到电路板上通常使用的相同的技术来执行两种安装操作。 通常的封装芯片可以用作顶部元件，从而降低组装成本，并允许通过选择封装的芯片来定制组件。 该组件实现了与使用预组装的堆叠芯片单元获得的效果相似的优点，但是不包含包装在封装芯片中的裸芯片的特殊处理费用。

公开(公告)号：US20030107118A1

公开(公告)日：2003-06-12

申请号：US10267450

申请日：2002-10-09

Applicant: Tessera, Inc.

Inventor： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell

IPC: H01L023/02

CPC classification number: H01L23/528 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract translation: 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，单个单元的多分支迹线通过断开各个分支而被选择性地中断，以便将芯片的芯片选择触点留在连接到不同芯片选择端子的不同单元中，从而将这些芯片连接到不同的垂直 巴士 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。