Invention Application
- Patent Title: Stacked packages
- Patent Title (中): 堆叠包
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Application No.: US10834342Application Date: 2004-04-28
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Publication No.: US20040203190A1Publication Date: 2004-10-14
- Inventor: L. Elliott Pflughaupt , David Gibson , Young-Gon Kim , Craig S. Mitchell
- Applicant: Tessera, Inc.
- Applicant Address: CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: CA San Jose
- Main IPC: H01L021/44
- IPC: H01L021/44

Abstract:
A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.
Public/Granted literature
- US06913949B2 Stacked packages Public/Granted day:2005-07-05
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