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公开(公告)号：US09646928B2
公开(公告)日：2017-05-09
申请号：US14208310
申请日：2014-03-13
发明人： Jiun Yi Wu , Hsueh-Lung Cheng , Shou-Yi Wang
CPC分类号： H01L24/03 , H01L21/76804 , H01L21/7685 , H01L21/76879 , H01L22/32 , H01L23/522 , H01L23/5226 , H01L23/562 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02313 , H01L2224/0239 , H01L2224/03416 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0392 , H01L2224/05022 , H01L2224/05024 , H01L2224/05091 , H01L2224/05147 , H01L2224/05562 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13024 , H01L2224/13147 , H01L2924/01029 , H01L2924/20643 , H01L2924/3512 , H01L2924/00014
摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.
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公开(公告)号：US11824032B2
公开(公告)日：2023-11-21
申请号：US17205669
申请日：2021-03-18
发明人： Wei-Yu Chen , Chi-Yang Yu , Kuan-Lin Ho , Chin-Liang Chen , Yu-Min Liang , Jiun Yi Wu
IPC分类号： H01L23/00 , H01L23/31 , H01L25/065 , H01L21/56
CPC分类号： H01L24/20 , H01L21/561 , H01L21/563 , H01L23/3185 , H01L23/3192 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L24/14 , H01L2224/13 , H01L2224/13024 , H01L2224/14131 , H01L2224/16145 , H01L2224/16227 , H01L2224/19 , H01L2224/2101 , H01L2224/221 , H01L2224/24137 , H01L2224/32225 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2924/1431 , H01L2924/1437
摘要： A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.
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公开(公告)号：US20150262933A1
公开(公告)日：2015-09-17
申请号：US14208310
申请日：2014-03-13
发明人： Jiun Yi Wu , Hsueh-Lung Cheng , Shou-Yi Wang
IPC分类号： H01L23/522 , H01L23/532 , H01L21/66 , H01L23/00 , H01L21/768
CPC分类号： H01L24/03 , H01L21/76804 , H01L21/7685 , H01L21/76879 , H01L22/32 , H01L23/522 , H01L23/5226 , H01L23/562 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02313 , H01L2224/0239 , H01L2224/03416 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0392 , H01L2224/05022 , H01L2224/05024 , H01L2224/05091 , H01L2224/05147 , H01L2224/05562 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13024 , H01L2224/13147 , H01L2924/01029 , H01L2924/20643 , H01L2924/3512 , H01L2924/00014
摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.
摘要翻译： 提供了半导体布置和形成方法。 半导体装置包括在至少第一电介质层和第二电介质层下面的金属迹线。 金属迹线通过第一介电层中的第一通孔和第二介电层中的第二通孔连接到球形连接。 金属轨迹在连接点处连接到测试焊盘，其中连接点在第一介电层下。 至少第一电介质层和第二电介质层上的金属迹线与金属迹线相比具有增加的稳定性和降低的对连接点，连接点，第一通孔或第二通孔中的至少一个的破裂敏感性 不在至少第一介电层和第二介电层下。
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公开(公告)号：US09812416B2
公开(公告)日：2017-11-07
申请号：US15589027
申请日：2017-05-08
发明人： Jiun Yi Wu , Hsueh-Lung Cheng , Shou-Yi Wang
IPC分类号： H01L21/4763 , H01L23/00 , H01L23/522 , H01L21/66 , H01L21/768
CPC分类号： H01L24/03 , H01L21/76804 , H01L21/7685 , H01L21/76879 , H01L22/32 , H01L23/522 , H01L23/5226 , H01L23/562 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02313 , H01L2224/0239 , H01L2224/03416 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/0392 , H01L2224/05022 , H01L2224/05024 , H01L2224/05091 , H01L2224/05147 , H01L2224/05562 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13024 , H01L2224/13147 , H01L2924/01029 , H01L2924/20643 , H01L2924/3512 , H01L2924/00014
摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.
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