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公开(公告)号:US12021079B2
公开(公告)日:2024-06-25
申请号:US17460049
申请日:2021-08-27
发明人: Yi-Chun Chen , Jih-Jse Lin , Ryan Chia-Jen Chen
IPC分类号: H01L27/088 , H01L21/306 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号: H01L27/0886 , H01L21/30608 , H01L21/823431 , H01L29/0649 , H01L29/6681 , H01L29/7851
摘要: A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.
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公开(公告)号:US11791403B2
公开(公告)日:2023-10-17
申请号:US17460208
申请日:2021-08-28
发明人: Ya-Yi Tsai , Yi-Chun Chen , Wei-Han Chen , Wei-Ting Guo , Shu-Yuan Ku
IPC分类号: H01L29/76 , H01L29/94 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/78
CPC分类号: H01L29/6681 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/7851
摘要: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
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公开(公告)号:US11437484B2
公开(公告)日:2022-09-06
申请号:US16390190
申请日:2019-04-22
发明人: Yi-Chun Chen , Tsung Fan Yin , Li-Te Hsu , Ying Ting Hsia , Yi-Wei Chiu
摘要: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
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公开(公告)号:US20240304620A1
公开(公告)日:2024-09-12
申请号:US18670223
申请日:2024-05-21
发明人: Yi-Chun Chen , Jih-Jse Lin , Ryan Chia-Jen Chen
IPC分类号: H01L27/088 , H01L21/306 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号: H01L27/0886 , H01L21/30608 , H01L21/823431 , H01L29/0649 , H01L29/6681 , H01L29/7851
摘要: A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.
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公开(公告)号:US20240112957A1
公开(公告)日:2024-04-04
申请号:US18153553
申请日:2023-01-12
IPC分类号: H01L21/8238 , H01L27/092
CPC分类号: H01L21/823842 , H01L27/0924
摘要: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.
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公开(公告)号:US20210249313A1
公开(公告)日:2021-08-12
申请号:US16787625
申请日:2020-02-11
发明人: Yi-Chun Chen , Ryan Chia-Jen Chen , Shu-Yuan Ku , Ya-Yi Tsai , I-Wei Yang
IPC分类号: H01L21/8238 , H01L27/092
摘要: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.
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公开(公告)号:US20190245055A1
公开(公告)日:2019-08-08
申请号:US16390190
申请日:2019-04-22
发明人: Yi-Chun Chen , Tsung Fan Yin , Li-Te Hsu , Ying Ting Hsia , Yi-Wei Chiu
CPC分类号: H01L29/4966 , H01L21/28088 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
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8.
公开(公告)号:US10269917B2
公开(公告)日:2019-04-23
申请号:US15297850
申请日:2016-10-19
发明人: Yi-Chun Chen , Tsung Fan Yin , Li-Te Hsu , Ying Ting Hsia , Yi-Wei Chiu
摘要: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
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公开(公告)号:US12034063B2
公开(公告)日:2024-07-09
申请号:US18232533
申请日:2023-08-10
发明人: Ya-Yi Tsai , Yi-Chun Chen , Wei-Han Chen , Wei-Ting Guo , Shu-Yuan Ku
IPC分类号: H01L29/76 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/94
CPC分类号: H01L29/6681 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/7851
摘要: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
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公开(公告)号:US20230387271A1
公开(公告)日:2023-11-30
申请号:US18232533
申请日:2023-08-10
发明人: Ya-Yi Tsai , Yi-Chun Chen , Wei-Han Chen , Wei-Ting Guo , Shu-Yuan Ku
IPC分类号: H01L29/66 , H01L27/088 , H01L29/78 , H01L21/8234 , H01L29/06
CPC分类号: H01L29/6681 , H01L27/0886 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/7851
摘要: A method of fabricating a semiconductor device is described. A plurality of semiconductor fins is formed in a first region on a substrate. An isolation region is formed around the plurality of semiconductor fins. Dummy fins are formed extending above the isolation region and laterally adjacent the plurality of semiconductor fins. A first etch is performed to etch the plurality of semiconductor fins such that a top surface of the plurality of semiconductor fins has a same height as a top surface of the isolation region. A second etch is performed selectively etching the isolation region to form a first recess in the isolation region laterally adjacent the semiconductor fins. A third etch is performed selectively etching the plurality of semiconductor fins to remove the plurality of semiconductor fins and to etch a second recess through the isolation region into the semiconductor substrate.
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