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公开(公告)号:US10298228B2
公开(公告)日:2019-05-21
申请号:US15902880
申请日:2018-02-22
发明人: Yang-Chi Yen , Bo-Ting Chen
IPC分类号: H03K17/693 , H03K19/173 , H01L27/118 , H01L27/092 , H04J1/02
摘要: A multiplexer circuit, of power supply (PS) voltages, includes: selectable finger circuits corresponding to the PS voltages, each selectable finger circuit: having an input node which is finger-circuit-specific and an output node which is common to the finger circuits; being configured to receive a corresponding one of the PS voltages from the input node and, if selected, provide a first version of the corresponding PS voltage to the output node. Each of the selectable finger circuits includes: a non-enhancement mode transistor of a first conductivity (C1) type (C1-type transistor) and enhancement mode first and second transistors of a second conductivity (C2) type (C2-type transistor) connected in series between the input node and the output node.
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公开(公告)号:US10128329B2
公开(公告)日:2018-11-13
申请号:US15242894
申请日:2016-08-22
发明人: Wan-Yen Lin , Wun-Jie Lin , Yu-Ti Su , Bo-Ting Chen , Jen-Chou Tseng , Kuo-Ji Chen , Sun-Jay Chang , Min-Chang Liang
IPC分类号: H01L29/06 , H01L21/76 , H01L27/02 , H01L27/088 , H01L29/66 , H01L29/78 , H01L21/265 , H01L21/761 , H01L21/8234
摘要: A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further includes implanting a first set of guard rings around a periphery of the core circuitry. The first set of guard rings has a first dopant type. Implanting the first set of guard rings includes implanting the first set of guard rings spaced from the doped region. The method further includes implanting a second set of guard rings having a second dopant type, wherein the second dopant type being opposite to the first dopant type. At least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings.
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公开(公告)号:US10979049B2
公开(公告)日:2021-04-13
申请号:US16789072
申请日:2020-02-12
发明人: Wan-Yen Lin , Yuan-Ju Chan , Bo-Ting Chen
IPC分类号: H03K19/003 , H03K19/0185
摘要: A buffer circuit includes an input terminal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, and the transition time of the output signal is based on a duration of a logic inversion of the input signal.
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公开(公告)号:US09117669B2
公开(公告)日:2015-08-25
申请号:US13723001
申请日:2012-12-20
发明人: Wun-Jie Lin , Bo-Ting Chen , Jen-Chou Tseng , Ming-Hsiang Song
IPC分类号: H01L27/10 , H01L29/861 , H01L21/02 , H01L27/02 , H01L27/06
CPC分类号: H01L27/0255 , H01L27/0629 , H01L27/2409 , H01L29/66136 , H01L29/861
摘要: A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region.
摘要翻译: 一种结构包括形成在衬底的第一鳍上的N +区,形成在衬底的第二鳍上的P +区,其中P +区和N +区形成二极管,在P +区和 N +区域和形成在浅沟槽隔离区域之间以及N +区域和P +区域之间的第一外延生长块区域,其中二极管的正向偏置电流流过浅沟槽隔离区域下方的路径。
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公开(公告)号:US20140252476A1
公开(公告)日:2014-09-11
申请号:US13789909
申请日:2013-03-08
发明人: Sun-Jay Chang , Ming-Hsiang Song , Jen-Chou Tseng , Wun-Jie Lin , Bo-Ting Chen
IPC分类号: H01L23/60
CPC分类号: H01L29/0692 , H01L21/2253 , H01L27/0255 , H01L29/6609 , H01L29/66795 , H01L29/785 , H01L29/861 , H01L29/868
摘要: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.
摘要翻译: 二极管包括具有平行于第一方向的纵向方向的第一组多个组合翅片,其中所述第一组合翼片包括第一导电类型的部分。 二极管还包括具有与第一方向平行的长度方向的第二组合翅片,其中第二组合翅片包括与第一导电类型相反的第二导电类型的部分。 隔离区域位于第一组合翅片和第二组合翅片之间。 第一和第二多个组合翅片形成二极管的阴极和阳极。 二极管被配置为具有在垂直于第一方向的第二方向上流动的电流,其中电流在阳极和阴极之间流动。
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公开(公告)号:US11966241B2
公开(公告)日:2024-04-23
申请号:US17650668
申请日:2022-02-11
发明人: Huan-Neng Chen , Yen-Lin Liu , Chia-Wei Hsu , Jo-Yu Wu , Chang-Fen Hu , Shao-Yu Li , Bo-Ting Chen
IPC分类号: G05F1/595 , G05F1/575 , H03K19/0175
CPC分类号: G05F1/595 , G05F1/575 , H03K19/017509
摘要: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
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公开(公告)号:US20230009027A1
公开(公告)日:2023-01-12
申请号:US17650668
申请日:2022-02-11
发明人: Huan-Neng Chen , Yen-Lin LIU , Chia-Wei Hsu , Jo-Yu Wu , CHANG-FEN HU , Shao-Yu Li , Bo-Ting Chen
IPC分类号: G05F1/595 , G05F1/575 , H03K19/0175
摘要: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
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公开(公告)号:US11545977B2
公开(公告)日:2023-01-03
申请号:US17227815
申请日:2021-04-12
发明人: Wan-Yen Lin , Yuan-Ju Chan , Bo-Ting Chen
IPC分类号: H03K19/003 , H03K19/0185
摘要: A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit includes a first transistor and an RC network including a resistor and a capacitor, the first transistor is coupled in series with the resistor between a power supply node and a reference node, and the buffer and the RC circuit are configured to generate an output signal based on the input signal.
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公开(公告)号:US20220415797A1
公开(公告)日:2022-12-29
申请号:US17571680
申请日:2022-01-10
发明人: Bo-Ting Chen
IPC分类号: H01L23/528 , H01L21/768
摘要: Systems and methods are provided for a multiple power supply mode input/output (IO) circuit of an integrated circuit that includes a plurality of power rails, one or more supply mode power rails being associated with each supply mode of the integrated circuit, and a core power rail being associated with core circuitry of the integrated circuit. The IO circuit may further include a plurality of chip connection points, each chip connection point being connected to one or more of the power rails, the chip connection points being configured for connection to one or more package connection points.
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公开(公告)号:US10269986B2
公开(公告)日:2019-04-23
申请号:US15074065
申请日:2016-03-18
发明人: Sun-Jay Chang , Ming-Hsiang Song , Jen-Chou Tseng , Wun-Jie Lin , Bo-Ting Chen
IPC分类号: H01L27/02 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/225 , H01L29/861 , H01L29/868
摘要: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.
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