公开(公告)号：US11621191B2

公开(公告)日：2023-04-04

申请号：US17135758

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuan-Yen Lo ,  Chia-Cheng Chang ,  Ming-Jhih Kuo ,  Chien-Yuan Chen

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/32

Abstract: In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.

公开(公告)号：US11022898B2

公开(公告)日：2021-06-01

申请号：US16656942

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lun Liu ,  Ming-Jhih Kuo ,  Yuan-Yen Lo

IPC: G03F7/20

Abstract: A method of evaluating a focus control of an extreme ultraviolet (EUV) lithography apparatus includes preparing a wafer exposed by using the EUV lithography apparatus. The wafer includes test patterns formed of a photoresist and having circular islands or holes prepared by multiple exposures of EUV at different foci of exposure. The method further includes measuring a roughness parameter of the test patterns and estimating a function representing a dependence of the roughness parameter on the focus. A best focus is estimated based on an extremum of the function. Exposure wafers are then exposed to EUV with the best focus. The exposure wafers include the test patterns. The roughness parameter for the test patterns on the exposure wafers obtained by exposing the exposure wafers at the best focus is periodically measured. An abnormality in focus is then determined based on the measured roughness parameter and the function.

公开(公告)号：US20170338146A1

公开(公告)日：2017-11-23

申请号：US15593149

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Sung Yen ,  Yu-Hsun Chen ,  Chen-Hau Wu ,  Chun-Kuang Chen ,  Ta-Ching Yu ,  Ken-Hsien Hsieh ,  Ming-Jhih Kuo ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/5283

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

公开(公告)号：US09711420B1

公开(公告)日：2017-07-18

申请号：US15069608

申请日：2016-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yen Lo ,  Chia-Chu Liu ,  Ming-Jhih Kuo

IPC: G03F1/00 ,  G03F7/20 ,  G03C5/00 ,  H01L21/66

CPC classification number: H01L22/20 ,  G03F7/70625 ,  G03F7/70641 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34

Abstract: A method includes processing a first silicon wafer using a first focus condition, the first silicon wafer comprising: a first test pattern and a second test pattern, the first test pattern and the second test pattern being different. The method further includes determining a first critical dimension for the first test pattern, determining a second critical dimension for the second test pattern, determining a delta focus value based on the first critical dimension and the second critical dimension, and processing a second silicon wafer with a second focus condition, the second focus condition based on the delta focus value.

公开(公告)号：US11862690B2

公开(公告)日：2024-01-02

申请号：US17239254

申请日：2021-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Wen Hsiao ,  Chun-Yen Tai ,  Yen-Hsin Liu ,  Ming-Jhih Kuo ,  Ming-Feng Shieh

IPC: H01L29/40 ,  H01L21/027 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/0273 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41791

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

公开(公告)号：US10451979B2

公开(公告)日：2019-10-22

申请号：US16029391

申请日：2018-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lun Liu ,  Ming-Jhih Kuo ,  Yuan-Yen Lo

IPC: G03F7/20

Abstract: A method of evaluating a focus control of an extreme ultraviolet (EUV) lithography apparatus includes preparing a wafer exposed by using the EUV lithography apparatus. The wafer includes test patterns formed of a photoresist and having circular islands or holes prepared by multiple exposures of EUV at different foci of exposure. The method further includes measuring a roughness parameter of the test patterns and estimating a function representing a dependence of the roughness parameter on the focus. A best focus is estimated based on an extremum of the function. Exposure wafers are then exposed to EUV with the best focus. The exposure wafers include the test patterns. The roughness parameter for the test patterns on the exposure wafers obtained by exposing the exposure wafers at the best focus is periodically measured. An abnormality in focus is then determined based on the measured roughness parameter and the function.

公开(公告)号：US10276377B2

公开(公告)日：2019-04-30

申请号：US15593149

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Sung Yen ,  Yu-Hsun Chen ,  Chen-Hau Wu ,  Chun-Kuang Chen ,  Ta-Ching Yu ,  Ken-Hsien Hsieh ,  Ming-Jhih Kuo ,  Ru-Gun Liu

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L23/528

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.