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    Method for patterning interconnects
    3.
    发明授权
    Method for patterning interconnects 有权

    公开(公告)号：US10276377B2

    公开(公告)日：2019-04-30

    申请号：US15593149

    申请日：2017-05-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Sung Yen ,  Yu-Hsun Chen ,  Chen-Hau Wu ,  Chun-Kuang Chen ,  Ta-Ching Yu ,  Ken-Hsien Hsieh ,  Ming-Jhih Kuo ,  Ru-Gun Liu

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L23/528

    Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

    Directional patterning methods
    4.
    发明授权
    Directional patterning methods 有权

    公开(公告)号：US10049918B2

    公开(公告)日：2018-08-14

    申请号：US15395310

    申请日：2016-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

    IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3115

    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

    Directional Patterning Methods
    5.
    发明申请
    Directional Patterning Methods 审中-公开

    公开(公告)号：US20180090370A1

    公开(公告)日：2018-03-29

    申请号：US15395310

    申请日：2016-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

    CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/31155

    Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

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