公开(公告)号：US20200098923A1

公开(公告)日：2020-03-26

申请号：US16696845

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20200294973A1

公开(公告)日：2020-09-17

申请号：US16889498

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L21/02 ,  H01L25/04 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

公开(公告)号：US20180301560A1

公开(公告)日：2018-10-18

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20190131274A1

公开(公告)日：2019-05-02

申请号：US15794286

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L25/04 ,  H01L21/02

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

公开(公告)号：US20180145176A1

公开(公告)日：2018-05-24

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.

公开(公告)号：US20150249141A1

公开(公告)日：2015-09-03

申请号：US14672298

申请日：2015-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsing YU ,  Chia-Wen LIU ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/16 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  Y10S438/931

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract translation: 提供晶体管和形成晶体管的方法。 该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。 使用具有低倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。 晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。 掺杂剂分布在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域。

公开(公告)号：US20220359754A1

公开(公告)日：2022-11-10

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

公开(公告)号：US20150194485A1

公开(公告)日：2015-07-09

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya DHANYAKUMAR ,  Wei-Hao WU ,  Tsung-Hsing YU ,  Chia-Wen LIU ,  Tzer-Min SHEN ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract translation: 设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。 因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。 外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。 可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。