公开(公告)号：US12243925B2

公开(公告)日：2025-03-04

申请号：US17869430

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US12176401B2

公开(公告)日：2024-12-24

申请号：US18446681

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US20240379812A1

公开(公告)日：2024-11-14

申请号：US18784647

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US12132112B2

公开(公告)日：2024-10-29

申请号：US17875561

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Ji-Cheng Chen ,  Weng Chang ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

公开(公告)号：US20240347392A1

公开(公告)日：2024-10-17

申请号：US18753130

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L21/28568

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20240282816A1

公开(公告)日：2024-08-22

申请号：US18654298

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions, the gate structure including: a gate dielectric material around each of the nanosheets; a work function material around the gate dielectric material; a liner material around the work function material, where the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along sidewalls of the nanosheets; and a gate electrode material around at least portions of the liner material.

公开(公告)号：US12068388B2

公开(公告)日：2024-08-20

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US20240154016A1

公开(公告)日：2024-05-09

申请号：US18414753

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/401 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/0673

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US11935937B2

公开(公告)日：2024-03-19

申请号：US17577169

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L21/02603 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

公开(公告)号：US20230387202A1

公开(公告)日：2023-11-30

申请号：US18359695

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L27/0924

Abstract: An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.