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    Semiconductor memory device and control method of semiconductor memory device
    1.
    发明授权
    Semiconductor memory device and control method of semiconductor memory device 有权

    公开(公告)号：US10424384B2

    公开(公告)日：2019-09-24

    申请号：US16114182

    申请日：2018-08-27

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yusuke Higashi ,  Tomoya Sanuki

    IPC: G11C11/34 ,  G11C16/26 ,  H01L27/102 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582

    Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190273090A1

    公开(公告)日：2019-09-05

    申请号：US16409637

    申请日：2019-05-10

    Applicant: Toshiba Memory Corporation

    Inventor： Yoshiaki FUKUZUMI ,  Hideaki Aochi ,  Mie Matsuo ,  Kenichiro Yoshii ,  Koichiro Shindo ,  Kazushige Kawasaki ,  Tomoya Sanuki

    IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/768 ,  H01L21/18 ,  H01L27/11582

    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11222900B2

    公开(公告)日：2022-01-11

    申请号：US16228867

    申请日：2018-12-21

    Applicant: Toshiba Memory Corporation

    Inventor： Yoshiro Shimojo ,  Tomoya Sanuki

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200043942A1

    公开(公告)日：2020-02-06

    申请号：US16228867

    申请日：2018-12-21

    Applicant: Toshiba Memory Corporation

    Inventor： Yoshiro SHIMOJO ,  Tomoya Sanuki

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.

    Semiconductor device with bonding pads and method of manufacturing the same
    9.
    发明授权
    Semiconductor device with bonding pads and method of manufacturing the same 有权

    公开(公告)号：US11257802B2

    公开(公告)日：2022-02-22

    申请号：US16549486

    申请日：2019-08-23

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Tomoya Sanuki

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L23/528

    Abstract: A semiconductor device includes: a first semiconductor substrate and a logic circuit provided on the first semiconductor substrate; a memory cell provided above the logic circuit and a second semiconductor substrate provided above the memory cell; a bonding pad provided above the second semiconductor substrate and electrically connected to the logic circuit; and a wiring provided above the second semiconductor substrate. The wiring is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

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