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公开(公告)号：US12087826B2
公开(公告)日：2024-09-10
申请号：US17816308
申请日：2022-07-29
Inventor： Yao-Wen Chang , Gung-Pei Chang , Ching-Sheng Chu , Chern-Yow Hsu
IPC: H01L29/26 , H01L21/02 , H01L21/768
CPC classification number: H01L29/26 , H01L21/02172 , H01L21/0228 , H01L21/02304 , H01L21/76816 , H01L21/76831 , H01L21/76871 , H01L21/76889
Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer.
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公开(公告)号：US20230389445A1
公开(公告)日：2023-11-30
申请号：US18364697
申请日：2023-08-03
Inventor： Yao-Wen Chang , Chung-Chiang Min , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsung-Hsueh Yang , Yuan-Tai Tseng , Sheng-Huang Huang , Chia-Hua Lin
Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.
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公开(公告)号：US20230345786A1
公开(公告)日：2023-10-26
申请号：US17890883
申请日：2022-08-18
Inventor： Ching Ju Yang , Yao-Wen Chang , Chih-Chung Lai
CPC classification number: H01L27/329 , H01L51/56
Abstract: An interconnect structure includes at least a first interconnect element and a second interconnect element. A conductive pad layer is disposed over, and electrically coupled to, the first interconnect element. A capping layer is disposed over the conductive pad layer. The capping layer includes titanium nitride. A dielectric layer is disposed over the capping layer. A conductive contact extends vertically through at least a first portion of the dielectric layer and the capping layer. The conductive contact is coupled to the first interconnect element through the conductive pad layer. A conductive via extends vertically through at least a second portion of the dielectric layer. The conductive via is coupled to the second interconnect element.
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公开(公告)号：US11532511B2
公开(公告)日：2022-12-20
申请号：US17017569
申请日：2020-09-10
Inventor： Gung-Pei Chang , Yao-Wen Chang , Hai-Dang Trinh
IPC: H01L23/48 , H01L23/52 , H01L21/768 , H01L21/285 , H01L21/02 , H01L21/311 , H01L23/00
Abstract: A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.
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公开(公告)号：US20220359609A1
公开(公告)日：2022-11-10
申请号：US17873338
申请日：2022-07-26
Inventor： Chia-Hua Lin , Hsun-Chung Kuang , Yu-Hsing Chang , Yao-Wen Chang
Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.
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Patent Agency Ranking
公开(公告)号：US20240387424A1
公开(公告)日：2024-11-21
申请号：US18782099
申请日：2024-07-24
Inventor： Julie Yang , Chii Ming Wu , Tzu-Chung Tsai , Yao-Wen Chang
IPC: H01L23/00
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.
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公开(公告)号：US12150394B2
公开(公告)日：2024-11-19
申请号：US17677506
申请日：2022-02-22
Inventor： Ching Ju Yang , Huan-Chieh Chen , Yao-Wen Chang
Abstract: The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.
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公开(公告)号：US20240371685A1
公开(公告)日：2024-11-07
申请号：US18775749
申请日：2024-07-17
Inventor： Yen-Liang Lin , Chia-Wen Zhong , Yao-Wen Chang , Min-Chang Ching , Kuo-Liang Lu , Cheng-Yuan Tsai , Ru-Liang Lee
IPC: H01L21/768 , H01J37/32 , H01L21/02 , H01L21/67 , H01L21/687
Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.
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公开(公告)号：US20240355358A1
公开(公告)日：2024-10-24
申请号：US18763154
申请日：2024-07-03
Inventor： Tzu-Yu Lin , Yao-Wen Chang
Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
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公开(公告)号：US12119035B2
公开(公告)日：2024-10-15
申请号：US18150281
申请日：2023-01-05
Inventor： Tzu-Yu Lin , Yao-Wen Chang
Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
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