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公开(公告)号：US20230258721A1
公开(公告)日：2023-08-17
申请号：US17671999
申请日：2022-02-15
IPC分类号： G01R31/319 , H03K3/037 , H03K5/26 , G01R31/317 , G01R31/3183
CPC分类号： G01R31/31922 , H03K3/037 , H03K5/26 , G01R31/31725 , G01R31/3191 , G01R31/318328
摘要： A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.
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2.发明申请公开(公告)号：US20210081594A1
公开(公告)日：2021-03-18
申请号：US17103724
申请日：2020-11-24
发明人： YUNG-HSU CHUANG , WEN-SHEN CHOU , JIE-REN HUANG , YU-TAO YANG , YUNG-CHOW PENG , YUN-RU CHEN
IPC分类号： G06F30/398 , G06F30/367 , G06F30/394 , G06F30/327 , G06F30/392 , G06F30/36
摘要： A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.
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公开(公告)号：US20200089837A1
公开(公告)日：2020-03-19
申请号：US16134224
申请日：2018-09-18
发明人： YU-TAO YANG , YUNG-CHOW PENG
IPC分类号： G06F17/50
摘要： A method for forming an integrated device includes the following operations. A first circuit layout is provided. The first circuit layout includes a first device and a connecting portion. A first voltage level is applied to the first circuit layout. The first circuit layout is analyzed according to the first voltage level to determine if a failing signal occurs in the first circuit layout. The first device is analyzed when the failing signal occurs. It is determined, according to a second voltage level, whether a violation occurs in the first device. The first circuit layout is modified when a violation occurs.
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公开(公告)号：US20200257326A1
公开(公告)日：2020-08-13
申请号：US16863057
申请日：2020-04-30
摘要： A bandgap reference circuit includes a current generating circuit, a switch circuit and a control circuit. The current generating circuit is triggered by a trigger signal, generated when the bandgap reference circuit starts up, to mirror a base current to generate a first current and a second current. The current generating circuit is arranged to output the first current when triggered by the triggered signal. The switch circuit is controlled by a switch control signal to be selectively coupled between the current generating circuit and a terminal coupled to a regulator. The switch circuit is arranged to, when coupled between the current generating circuit and the terminal, allow the current generating circuit to output the second current to the terminal and accordingly provide a bandgap voltage. When the first current reduces to a predetermined level, the control circuit activates generation of the switch control signal to control the switch circuit.
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公开(公告)号：US20180097519A1
公开(公告)日：2018-04-05
申请号：US15282342
申请日：2016-09-30
发明人： YUNG-CHOW PENG , MAO-HSUAN CHOU
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A level shifter operating between a first power domain under a first supply voltage and a second power domain under a second supply voltage is provided. The level shifter includes a latch, formed by a first transistor and a second transistor, configured to store data and operate in the second power domain. The level shifter further includes a third transistor configured to be biased at the first supply voltage, and a current source configured to generate a current in response to the first supply voltage. The current flows towards the latch, and the magnitude of the current is positively correlated with the first supply voltage. In response to a first asserted state of the first supply voltage, the third transistor dominates over the current source in toggling the data and, in response to a second asserted state of the first supply voltage, the current source dominates over the third transistor in toggling the data. The second asserted state is lower in voltage level than the first asserted state.
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公开(公告)号：US20180006163A1
公开(公告)日：2018-01-04
申请号：US15200424
申请日：2016-07-01
发明人： SZU-LIN LIU , JAW-JUINN HORNG , YUNG-CHOW PENG
IPC分类号： H01L29/94 , H01L29/08 , H01L21/265 , H01L21/266 , H03K17/687 , H01L29/66
摘要： A metal-oxide-semiconductor (MOS) capacitor is disclosed. The MOS capacitor includes a front-end-of-the-line (FEOL) field effect transistor (FET), and a plurality of middle-end-of-the-line (MEOL) conductive structures. The FEOL FET includes a source region and a drain region positioned in a semiconductor substrate, and a gate over the semiconductor substrate. The plurality of MEOL conductive structures is disposed on a top surface of the gate. At least one of the MEOL conductive structures is electrically disconnected from a back-end-of-the-line (BEOL) metal layer. A semiconductor fabrication method and a MOS capacitor circuit are also disclosed.
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公开(公告)号：US20210090989A1
公开(公告)日：2021-03-25
申请号：US17115351
申请日：2020-12-08
发明人： TAI-YI CHEN , YUNG-CHOW PENG , CHUNG-CHIEH YANG
IPC分类号： H01L23/522 , H03M1/38 , H01L23/552
摘要： An integrated circuit structure includes a first conductive plate, a second conductive plate, a plurality of conductive lines, and a plurality of conductive vias. The first conductive plate is disposed in a first layer on a semiconductor substrate. The second conductive plate is disposed in a second layer on the semiconductor substrate. The plurality of conductive lines are disposed in the first layer for surrounding the first conductive plate. The plurality of conductive vias are arranged to couple the plurality of conductive lines to the second conductive plate. The second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.
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公开(公告)号：US20150268297A1
公开(公告)日：2015-09-24
申请号：US14222240
申请日：2014-03-21
IPC分类号： G01R31/28
CPC分类号： G01R27/28 , H03F3/45475 , H03F2200/261 , H03F2200/411 , H03F2203/45138 , H03F2203/45528 , H03F2203/45594
摘要： A circuit for measuring the gain of an operational amplifier is provided. The circuit comprises a first operational amplifier, a first resistive device and a second resistive device. The first operational amplifier has an original gain and includes a first input terminal and a second input terminal. The first resistive device is coupled between the first input terminal and the second input terminal of the first operational amplifier. The second resistive device is coupled to the second input terminal of the first operational amplifier. The first resistive device and the second resistive device are configured to reduce a predetermined amount of gain from the original gain of the first operational amplifier.
摘要翻译： 提供了一种用于测量运算放大器的增益的电路。 电路包括第一运算放大器，第一电阻器件和第二电阻器件。 第一运算放大器具有原始增益并包括第一输入端和第二输入端。 第一电阻器件耦合在第一运算放大器的第一输入端和第二输入端之间。 第二电阻器件耦合到第一运算放大器的第二输入端。 第一电阻装置和第二电阻装置被配置为从第一运算放大器的原始增益减小预定量的增益。
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公开(公告)号：US20150035568A1
公开(公告)日：2015-02-05
申请号：US13956838
申请日：2013-08-01
发明人： YUNG-CHOW PENG , AMIT KUNDU , SZU-LIN LIU , JAW-JUINN HORNG
IPC分类号： H03K3/011 , H01L27/088
CPC分类号： H01L27/088 , G01K7/01 , H01L23/34 , H01L27/0251 , H01L27/0886 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.
摘要翻译： 具有温度检测器的电路包括第一FET和第二FET。 第一和第二FET中的每一个具有非平面结构的沟道结构。 第二FET紧邻第一FET。 第二FET的栅极与第一FET分离，第二FET的源极和漏极短路在一起。 第二FET的栅极上的两个端子之间的第二FET的栅极的电阻随着第一FET的局部温度而变化。
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公开(公告)号：US20240363523A1
公开(公告)日：2024-10-31
申请号：US18769412
申请日：2024-07-11
发明人： TAI-YI CHEN , YUNG-CHOW PENG , CHUNG-CHIEH YANG
IPC分类号： H01L23/522 , H01L23/552 , H03M1/38
CPC分类号： H01L23/5225 , H01L23/5223 , H01L23/5226 , H01L23/552 , H01L28/40 , H01L28/60 , H01L28/86 , H01L28/92 , H03M1/38
摘要： An integrated circuit structure includes: a first capacitor structure, disposed over a semiconductor substrate and including a plurality of capacitors; a second capacitor structure, adjacent to the first capacitor structure; a first conductive plate, disposed over a first end of the second capacitor structure, the first conductive plate having a lateral side facing a lateral side of each of the first and second capacitor structures; and a second conductive plate, disposed over and across at least one of the first capacitor structure and the second capacitor structure.
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