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公开(公告)号：US20230401373A1
公开(公告)日：2023-12-14
申请号：US18362842
申请日：2023-07-31
Inventor： Kam-Tou SIO , Jiann-Tyng TZENG
IPC: G06F30/394 , G03F1/36 , G06F30/392 , G06F30/3947 , G06F30/3953
CPC classification number: G06F30/394 , G03F1/36 , G06F30/392 , G06F30/3947 , G06F30/3953 , G06F2111/04
Abstract: A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.
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公开(公告)号：US20230282639A1
公开(公告)日：2023-09-07
申请号：US18317440
申请日：2023-05-15
Inventor： Kam-Tou SIO , Chih-Liang CHEN , Charles Chew-Yuen YOUNG , Hui-Zhong ZHUANG , Jiann-Tyng TZENG , Yi-Hsun CHIU
IPC: H01L27/085 , H01L27/092 , H01L27/02 , H01L27/118
CPC classification number: H01L27/085 , H01L27/092 , H01L27/0207 , H01L27/11807 , H01L27/118 , H01L21/823892
Abstract: A method of forming an integrated circuit structure includes generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure. The generating the first well layout pattern includes generating a first layout pattern having a first width, and corresponding to fabricating a first portion of the first well, and generating a second layout pattern having a second width and corresponding to fabricating a second portion of the first well. The method further includes generating a first implant layout pattern having a third width and corresponding to fabricating a first set of implants in the first portion of the first well, generating a second implant layout pattern having a fourth width and corresponding to fabricating a second set of implants in the second portion of the first well, and manufacturing the integrated circuit structure based on the above layout patterns.
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公开(公告)号：US20230275090A1
公开(公告)日：2023-08-31
申请号：US17838090
申请日：2022-06-10
Inventor： Jiann-Tyng TZENG , Kam-Tou SIO , Shang-Wei FANG , Chun-Yen LIN , Sheng-Feng HUANG , Yi-Kan CHENG , Lee-Chung LU
IPC: H01L27/092 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/786 , H01L21/8238 , H01L29/66
CPC classification number: H01L27/0922 , H01L23/5286 , H01L29/0665 , H01L29/42392 , H01L29/41733 , H01L29/78618 , H01L29/78696 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823871 , H01L29/66742
Abstract: A semiconductor device includes a first cell in a first row, wherein the first row extends in a first direction, the first cell having a first cell height measured in a second direction perpendicular to the first direction. The semiconductor device further includes a second cell in the first row, wherein the second cell has a second cell height measured in the second direction, the second cell height is less than the first cell height. The second cell includes a first active region having a first width measured in the second direction, and a second active region having a second width measured in the second direction, wherein the second width is different from the first width.
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公开(公告)号：US20220336343A1
公开(公告)日：2022-10-20
申请号：US17853386
申请日：2022-06-29
Inventor： Kam-Tou SIO , Cheng-Chi CHUANG , Chih-Ming LAI , Jiann-Tyng TZENG , Wei-Cheng LIN , Lipen YUAN
IPC: H01L23/522 , H01L23/528 , H01L27/092 , H01L21/8238 , H01L21/768 , G06F30/394
Abstract: A method of manufacturing an integrated circuit (IC) structure includes forming an opening in a first dielectric material between a first gate structure and a second gate structure by removing a portion of the first dielectric material overlying a fin structure; filling at least part of the opening with a second dielectric material; and forming a contact overlying the fin structure and the second dielectric material.
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公开(公告)号：US20230411389A1
公开(公告)日：2023-12-21
申请号：US18447750
申请日：2023-08-10
Inventor： Te-Hsin CHIU , Kam-Tou SIO , Shang-Wei FANG , Wei-Cheng LIN , Jiann-Tyng TZENG
IPC: H01L27/088 , H01L29/06 , G06F30/392 , H01L29/78 , H01L21/8234 , H01L21/033 , H01L29/66
CPC classification number: H01L27/0886 , H01L29/0665 , G06F30/392 , H01L29/785 , H01L21/823431 , H01L21/0334 , H01L29/66795 , H01L2029/7858
Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
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Patent Agency Ranking
公开(公告)号：US20230245970A1
公开(公告)日：2023-08-03
申请号：US18298172
申请日：2023-04-10
Inventor： Te-Hsin CHIU , Kam-Tou SIO , Shih-Wei PENG , Wei-Cheng LIN , Jiann-Tyng TZENG
IPC: H01L23/528 , H01L21/8238 , H01L27/092
CPC classification number: H01L23/5286 , H01L21/823871 , H01L27/092
Abstract: A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.
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公开(公告)号：US20220130822A1
公开(公告)日：2022-04-28
申请号：US17345452
申请日：2021-06-11
Inventor： Te-Hsin CHIU , Kam-Tou SIO , Shang-Wei FANG , Wei-Cheng LIN , Jiann-Tyng TZENG
IPC: H01L27/088 , H01L29/06 , G06F30/392 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L21/033
Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
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公开(公告)号：US20210272605A1
公开(公告)日：2021-09-02
申请号：US17127091
申请日：2020-12-18
Inventor： Shih-Wei PENG , Jiann-Tyng TZENG , Kam-Tou SIO
IPC: G11C5/14 , H01L23/50 , H01L23/538 , G11C5/06
Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.
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公开(公告)号：US20200335507A1
公开(公告)日：2020-10-22
申请号：US16918798
申请日：2020-07-01
Inventor： Chih-Liang CHEN , Chih-Ming LAI , Charles Chew-Yuen YOUNG , Chin-Yuan TSENG , Jiann-Tyng TZENG , Kam-Tou SIO , Ru-Gun LIU , Wei-Liang LIN , L. C. CHOU
IPC: H01L27/11 , H01L21/308 , H01L27/088 , H01L29/66 , H01L29/78 , H01L21/8234
Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(≈90%)*T1)≤Pmin≤(Gmin+(≈110%)*T1).
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公开(公告)号：US20200134119A1
公开(公告)日：2020-04-30
申请号：US16556928
申请日：2019-08-30
Inventor： Kam-Tou SIO , Jiann-Tyng TZENG
Abstract: A method of generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row abutting the first row. The first row and the second row extend along a first direction and are laid out relative to a routing grid including first routing tracks along the first direction and second routing tracks along a second direction perpendicular to the first direction. First cell pins are placed within each first cell extending along second routing tracks. Second cell pins are placed over selected via placement points in each second cell. At least one second cell pin extends along a corresponding second routing track across a boundary of a corresponding second cell and into a corresponding first cell abutting the corresponding second cell.
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