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    Semiconductor arrangement and formation thereof
    2.
    发明授权
    Semiconductor arrangement and formation thereof 有权

    公开(公告)号：US10177242B2

    公开(公告)日：2019-01-08

    申请号：US15640635

    申请日：2017-07-03

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Tai-I Yang ,  Tien-Lu Lin ,  Wai-Yi Lien ,  Chih-Hao Wang ,  Jiun-Peng Wu

    IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02 ,  H01L21/4757 ,  H01L29/40

    摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

    Semiconductor arrangement and formation thereof
    3.
    发明授权
    Semiconductor arrangement and formation thereof 有权
    半导体装置及其形成

    公开(公告)号：US09373544B2

    公开(公告)日：2016-06-21

    申请号：US14208157

    申请日：2014-03-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

    发明人： Tai-I Yang ,  Tien-Lu Lin ,  Wai-Yi Lien ,  Chih-Hao Wang ,  Jiun-Peng Wu

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/47573 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

    摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

    摘要翻译： 提供了半导体布置和形成方法。 半导体装置包括与第一有源区的基本上平面的第一顶表面接触的导电接触，第一对准间隔物之间​​的接触和与第一对准间隔物接触的接触，以及具有基本上垂直的外表面的第二对准隔离物。 形成在第一对准间隔件和第二对准间隔件之间的接触件具有更理想的接触形状，然后形成在不具有基本上垂直的外表面的对准间隔件之间的接触。 与基本上不平面的有源区域相比，第一有源区域的基本平坦的表面指示第一有源区域的基本上未损坏的结构。 与受损的第一有效区域相比，基本上未损坏的第一有效区域具有更大的接触面积和更低的接触电阻。

    SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
    4.
    发明申请
    SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF 有权
    半导体布置及其形成

    公开(公告)号：US20150262876A1

    公开(公告)日：2015-09-17

    申请号：US14208157

    申请日：2014-03-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

    发明人： Tai-I Yang ,  Tien-Lu Lin ,  Wai-Yi Lien ,  Chih-Hao Wang ,  Jiun-Peng Wu

    IPC分类号： H01L21/768 ,  H01L23/544 ,  H01L29/66 ,  H01L29/423

    CPC分类号： H01L29/66545 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/47573 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

    摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

    摘要翻译： 提供了半导体布置和形成方法。 半导体装置包括与第一有源区的基本上平面的第一顶表面接触的导电接触，第一对准间隔物之间​​的接触和与第一对准间隔物接触的接触，以及具有基本上垂直的外表面的第二对准隔离物。 形成在第一对准间隔件和第二对准间隔件之间的接触件具有更理想的接触形状，然后形成在不具有基本上垂直的外表面的对准间隔件之间的接触。 与基本上不平面的有源区域相比，第一有源区域的基本平坦的表面指示第一有源区域的基本上未损坏的结构。 与受损的第一有效区域相比，基本上未损坏的第一有效区域具有更大的接触面积和更低的接触电阻。

    Semiconductor arrangement and formation thereof
    8.
    发明授权
    Semiconductor arrangement and formation thereof 有权

    公开(公告)号：US10680078B2

    公开(公告)日：2020-06-09

    申请号：US16240887

    申请日：2019-01-07

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Tai-I Yang ,  Tien-Lu Lin ,  Wai-Yi Lien ,  Chih-Hao Wang ,  Jiun-Peng Wu

    IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L21/4757 ,  H01L29/40

    摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

    Semiconductor arrangement and formation thereof
    10.
    发明授权
    Semiconductor arrangement and formation thereof 有权
    半导体装置及其形成

    公开(公告)号：US09349690B2

    公开(公告)日：2016-05-24

    申请号：US14208096

    申请日：2014-03-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

    发明人： Yu-Chieh Liao ,  Cheng-Chi Chuang ,  Tai-I Yang ,  Tien-Lu Lin ,  Yung-Hsu Wu

    IPC分类号： H01L21/311 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.

    摘要翻译： 提供了半导体装置和形成方法。 半导体装置包括互连，其包括由第二金属层包围的互连金属插塞。 互连件邻近电介质的侧壁，使得气隙在电介质的互连件和侧壁之间。 保护屏障在互连和气隙之上，并且与电介质顶表面直接物理接触。 由第二金属层包围的互连金属插塞不比不被第二金属层包围的互连金属插塞容易受损。 与不与电介质直接物理接触的保护屏障的半导体装置相比，与电介质直接物理接触的保护屏障减少了寄生电容，这降低了半导体装置的RC延迟。