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公开(公告)号：US20140252428A1
公开(公告)日：2014-09-11
申请号：US13789831
申请日：2013-03-08
CPC分类号： H01L21/823431 , H01L21/0206 , H01L21/30604 , H01L21/3083 , H01L21/31051 , H01L21/31111 , H01L21/76224 , H01L29/6653 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope.
摘要翻译： 集成电路结构包括半导体衬底，延伸到半导体衬底中的绝缘区域和绝缘区域的两个相对部分之间的半导体衬底。 半导体条包括高于绝缘区的顶表面的上部和绝缘区中的下部。 下部具有侧壁，该侧壁包括具有第一斜面的第一侧壁部分和在第一侧壁部分上并连接到第一侧壁部分的第二侧壁部分。 第二侧壁部分具有小于第一斜面的第二斜面。
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公开(公告)号：US20150104913A1
公开(公告)日：2015-04-16
申请号：US14052160
申请日：2013-10-11
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/02636 , H01L21/3065 , H01L21/76254 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823821 , H01L29/41775 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795
摘要： A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
摘要翻译： 一种方法包括分别在半导体衬底的第一部分和第二部分上形成第一栅极堆叠和第二栅极堆叠，掩蔽半导体衬底的第一部分，并掩蔽半导体衬底的第一部分， 用蚀刻调谐元件注入半导体衬底的第二部分。 同时蚀刻半导体衬底的第一部分和第二部分，以在半导体衬底中分别形成第一开口和第二开口。 该方法还包括在第一开口中外延生长第一半导体区域，并且在第二开口中外延生长第二半导体区域。
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公开(公告)号：US09870954B2
公开(公告)日：2018-01-16
申请号：US15013585
申请日：2016-02-02
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/322 , H01L21/8238 , H01L21/8234 , H01L21/3065 , H01L29/66 , H01L21/762 , H01L21/02 , H01L29/417
CPC分类号： H01L21/823814 , H01L21/02636 , H01L21/3065 , H01L21/76254 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823821 , H01L29/41775 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795
摘要： A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
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公开(公告)号：US09263551B2
公开(公告)日：2016-02-16
申请号：US14052160
申请日：2013-10-11
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/322 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L21/3065 , H01L21/762
CPC分类号： H01L21/823814 , H01L21/02636 , H01L21/3065 , H01L21/76254 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823821 , H01L29/41775 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795
摘要： A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
摘要翻译： 一种方法包括分别在半导体衬底的第一部分和第二部分上形成第一栅极堆叠和第二栅极堆叠，掩蔽半导体衬底的第一部分，并掩蔽半导体衬底的第一部分， 用蚀刻调谐元件注入半导体衬底的第二部分。 同时蚀刻半导体衬底的第一部分和第二部分，以在半导体衬底中分别形成第一开口和第二开口。 该方法还包括在第一开口中外延生长第一半导体区域，并且在第二开口中外延生长第二半导体区域。
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公开(公告)号：US20160155672A1
公开(公告)日：2016-06-02
申请号：US15013585
申请日：2016-02-02
IPC分类号： H01L21/8238 , H01L21/02 , H01L29/417 , H01L29/66
CPC分类号： H01L21/823814 , H01L21/02636 , H01L21/3065 , H01L21/76254 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823821 , H01L29/41775 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795
摘要： A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
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公开(公告)号：US20160027903A1
公开(公告)日：2016-01-28
申请号：US14876398
申请日：2015-10-06
IPC分类号： H01L29/66 , H01L21/308 , H01L21/311 , H01L21/3105 , H01L21/02 , H01L21/306 , H01L21/762
CPC分类号： H01L21/823431 , H01L21/0206 , H01L21/30604 , H01L21/3083 , H01L21/31051 , H01L21/31111 , H01L21/76224 , H01L29/6653 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.
摘要翻译： 一种方法包括蚀刻半导体衬底以形成半导体条和在该半导体条的相对的侧壁上的沟槽。 间隔物形成在半导体条的侧壁上，该侧壁用作蚀刻掩模以将沟槽向下延伸到半导体衬底中。 将介电材料填充到沟槽中，然后平坦化以在沟槽中形成绝缘区域。 绝缘区域是凹进的。 在凹陷之后，绝缘区域的顶表面低于半导体条的顶表面，并且可以在其上形成栅极结构。
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公开(公告)号：US09698055B2
公开(公告)日：2017-07-04
申请号：US14876398
申请日：2015-10-06
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/308 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/762
CPC分类号： H01L21/823431 , H01L21/0206 , H01L21/30604 , H01L21/3083 , H01L21/31051 , H01L21/31111 , H01L21/76224 , H01L29/6653 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： A method includes etching a semiconductor substrate to form a semiconductor strip and trenches on opposite sidewalls of the semiconductor strip. A spacer is formed on a sidewall of the semiconductor strip which is used as an etching mask to extend the trenches down into the semiconductor substrate. A dielectric material is filled into the trenches and then planarized to form insulation regions in the trenches. The insulation regions are recessed. After the recessing, top surfaces of the insulation regions are lower than a top surface of the semiconductor strip and a gate structure may be formed thereon.
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公开(公告)号：US09159832B2
公开(公告)日：2015-10-13
申请号：US13789831
申请日：2013-03-08
IPC分类号： H01L29/76 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/308
CPC分类号： H01L21/823431 , H01L21/0206 , H01L21/30604 , H01L21/3083 , H01L21/31051 , H01L21/31111 , H01L21/76224 , H01L29/6653 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope.
摘要翻译： 集成电路结构包括半导体衬底，延伸到半导体衬底中的绝缘区域和绝缘区域的两个相对部分之间的半导体衬底。 半导体条包括高于绝缘区的顶表面的上部和绝缘区中的下部。 下部具有侧壁，该侧壁包括具有第一斜面的第一侧壁部分和在第一侧壁部分上并连接到第一侧壁部分的第二侧壁部分。 第二侧壁部分具有小于第一斜面的第二斜面。
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