知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.017 秒)

    Lithographic Technique for Feature Cut by Line-End Shrink
    3.
    发明申请
    Lithographic Technique for Feature Cut by Line-End Shrink 有权
    通过线端收缩切割特征的平版印刷技术

    公开(公告)号：US20160181110A1

    公开(公告)日：2016-06-23

    申请号：US14835495

    申请日：2015-08-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yung-Sung Yen ,  Chun-Kuang Chen ,  Ko-Bin Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/768 ,  H01L21/31

    CPC分类号： H01L21/0274 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877

    摘要： A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

    摘要翻译： 提供了用于图案化诸如集成电路工件的工件的技术。 在示例性实施例中，该方法包括接收指定要在工件上形成的多个特征的数据集。 基于多个特征的第一组特征来执行工件的硬掩模的第一图案化，并且第一间隔物材料沉积在图案化硬掩模的侧壁上。 基于第二组特征进行第二图案化，并且第二间隔物材料沉积在第一间隔物材料的侧壁上。 基于第三组特征来执行第三图案化。 使用由图案化硬掩模层，第一间隔物材料或第二间隔物材料中的至少一个的剩余部分限定的图案来选择性地处理工件的一部分。

    Mask assignment optimization
    4.
    发明授权
    Mask assignment optimization 有权
    掩模分配优化

    公开(公告)号：US09003336B2

    公开(公告)日：2015-04-07

    申请号：US13781980

    申请日：2013-03-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Wen-Chun Huang ,  Ken-Hsien Hsieh ,  Ming-Hui Chih ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Ko-Bin Kao ,  Chii-Ping Chen ,  Dian-Hau Chen ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    IPC分类号： G06F17/50 ,  H01L21/768

    CPC分类号： G06F17/50 ,  G03F1/44 ,  H01L21/76816

    摘要： A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.

    摘要翻译： 用于优化多个图案处理的掩模分配的方法包括：通过计算系统，基于与通孔相互作用的金属线，确定要在两个金属层之间形成的多个通孔中的哪一个是至关重要的，确定对准树的覆盖控制误差 其定义用于形成两个金属层和通孔的掩​​模对准，并且设置用于通孔的对准树和掩模分配，以便最大化对具有较小重叠控制误差的掩模上的关键通孔的放置，以形成相关的掩模 金属线。

    Lithographic technique for feature cut by line-end shrink
    7.
    发明授权
    Lithographic technique for feature cut by line-end shrink 有权

    公开(公告)号：US10763113B2

    公开(公告)日：2020-09-01

    申请号：US16541340

    申请日：2019-08-15

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yung-Sung Yen ,  Chun-Kuang Chen ,  Ko-Bin Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

    摘要： A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.

    Methods of patterning small via pitch dimensions
    8.
    发明授权
    Methods of patterning small via pitch dimensions 有权
    通过间距尺寸图案化的方法

    公开(公告)号：US09099530B2

    公开(公告)日：2015-08-04

    申请号：US14273080

    申请日：2014-05-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Yi Lin ,  Jiing-Feng Yang ,  Tzu-Hao Huang ,  Chih-Hao Hsieh ,  Dian-Hau Chen ,  Hsiang-Lin Chen ,  Ko-Bin Kao ,  Yung-Shih Cheng

    IPC分类号： H01B13/00 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/308

    CPC分类号： H01L21/76805 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76877

    摘要： Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

    摘要翻译： 描述集成电路方法。 所述方法包括提供包括用于两个通孔开口的两个主要特征的光掩模，并且还包括连接两个主要特征的光学邻近校正（OPC）特征; 在基板上形成硬掩模层，所述硬掩模层包括两个沟槽开口; 使用所述光掩模在所述硬掩模层上形成图案化的抗蚀剂层，其中所述图案化抗蚀剂层包括分别具有与所述硬掩模层的两个沟槽开口对准的两个端部的花生形开口; 以及使用所述硬掩模层和所述图案化抗蚀剂层作为组合蚀刻掩模对所述衬底执行第一蚀刻工艺。

    Lithographic technique for feature cut by line-end shrink
    10.
    发明授权
    Lithographic technique for feature cut by line-end shrink 有权

    公开(公告)号：US10388523B2

    公开(公告)日：2019-08-20

    申请号：US15990147

    申请日：2018-05-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yung-Sung Yen ,  Chun-Kuang Chen ,  Ko-Bin Kao ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

    IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

    摘要： A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.