-
公开(公告)号：US20230387071A1
公开(公告)日：2023-11-30
申请号：US18359416
申请日：2023-07-26
发明人： Kai-Tai Chang , Tung Ying Lee
IPC分类号： H01L23/00 , H01L21/66 , H01L21/68 , H01L23/544 , H01L21/67
CPC分类号： H01L24/80 , H01L22/12 , H01L21/68 , H01L23/544 , H01L21/67092 , H01L21/681 , H01L2224/80125 , H01L2223/54426 , H01L2224/8013
摘要： A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.
-
公开(公告)号：US11756921B2
公开(公告)日：2023-09-12
申请号：US17369146
申请日：2021-07-07
发明人： Kai-Tai Chang , Tung Ying Lee
IPC分类号： H01L23/00 , H01L21/66 , H01L21/68 , H01L23/544 , H01L21/67
CPC分类号： H01L24/80 , H01L21/67092 , H01L21/68 , H01L21/681 , H01L22/12 , H01L23/544 , H01L2223/54426 , H01L2224/8013 , H01L2224/80125
摘要： A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.
-
公开(公告)号：US11672186B2
公开(公告)日：2023-06-06
申请号：US17369484
申请日：2021-07-07
发明人： Chien-Min Lee , Shy-Jay Lin , Yen-Lin Huang , MingYuan Song , Tung Ying Lee
CPC分类号： H01L43/04 , H01L27/228 , H01L43/10 , H01L43/14
摘要： Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.
-
公开(公告)号：US20220336742A1
公开(公告)日：2022-10-20
申请号：US17383726
申请日：2021-07-23
发明人： Tung Ying Lee , Shao-Ming Yu , Kai-Tai Chang
摘要： A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
-
公开(公告)号：US11271095B2
公开(公告)日：2022-03-08
申请号：US16910662
申请日：2020-06-24
发明人： Yu-Lien Huang , Tung Ying Lee
IPC分类号： H01L29/66 , H01L21/311 , H01L29/78 , H01L21/768 , H01L21/285 , H01L21/306 , H01L21/8234 , H01L27/088 , H01L29/45
摘要： An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
-
公开(公告)号：US11244867B2
公开(公告)日：2022-02-08
申请号：US16535975
申请日：2019-08-08
发明人： Tzu-Chung Wang , Tung Ying Lee
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088
摘要： A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.
-
公开(公告)号：US11183584B2
公开(公告)日：2021-11-23
申请号：US16746127
申请日：2020-01-17
发明人： Meng-Hsuan Hsiao , Tung Ying Lee , Wei-Sheng Yun , Jin Cai
IPC分类号： H01L29/786 , H01L29/423 , H01L29/16 , H01L29/66 , H01L27/092 , H01L29/06 , H01L21/762 , H01L21/02 , H01L21/306
摘要： A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction. Each of the first semiconductor layers at the first portion of the first semiconductor layers have a substantially same thickness.
-
公开(公告)号：US20210336138A1
公开(公告)日：2021-10-28
申请号：US16992210
申请日：2020-08-13
发明人： Tung Ying Lee , Yu Chao Lin , Shao-Ming Yu
IPC分类号： H01L45/00
摘要： A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
-
公开(公告)号：US20210313455A1
公开(公告)日：2021-10-07
申请号：US17352507
申请日：2021-06-21
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/775 , H01L21/8238 , H01L21/02 , H01L21/8234
摘要： The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
-
公开(公告)号：US20210098452A1
公开(公告)日：2021-04-01
申请号：US17121495
申请日：2020-12-14
发明人： Tung Ying Lee , Wen-Huei Guo , Chih-Hao Chang , Shou-Zen Chang
IPC分类号： H01L27/088 , H01L29/66 , H01L21/84 , H01L21/8234 , H01L27/06 , H01L29/06 , H01L27/02 , H01L29/78
摘要： Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.
-
-
-
-
-
-
-
-
-
搜索结果
88 条记录 (耗时 0.029 秒)
