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公开(公告)号：US11245024B2
公开(公告)日：2022-02-08
申请号：US16844809
申请日：2020-04-09
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , NATIONAL TAIWAN UNIVERSITY , NATIONAL TAIWAN NORMAL UNIVERSITY
发明人： Tung-Ying Lee , Tse-An Chen , Tzu-Chung Wang , Miin-Jang Chen , Yu-Tung Yin , Meng-Chien Yang
IPC分类号： H01L21/28 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/66 , H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02
摘要： A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.
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公开(公告)号：US11244867B2
公开(公告)日：2022-02-08
申请号：US16535975
申请日：2019-08-08
发明人： Tzu-Chung Wang , Tung Ying Lee
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088
摘要： A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.
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公开(公告)号：US20210313455A1
公开(公告)日：2021-10-07
申请号：US17352507
申请日：2021-06-21
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/775 , H01L21/8238 , H01L21/02 , H01L21/8234
摘要： The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
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公开(公告)号：US10797174B2
公开(公告)日：2020-10-06
申请号：US16104692
申请日：2018-08-17
发明人： Kai-Tai Chang , Tung Ying Lee , Wei-Sheng Yun , Tzu-Chung Wang , Chia-Cheng Ho , Ming-Shiang Lin , Tzu-Chiang Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762 , H01L21/768 , H01L21/8238 , H01L21/033 , H01L21/02 , H01L23/532
摘要： A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
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公开(公告)号：US20200273997A1
公开(公告)日：2020-08-27
申请号：US16874539
申请日：2020-05-14
发明人： Feng Yuan , Ming-Shiang Lin , Chia-Cheng Ho , Jin Cai , Tzu-Chung Wang , Tung Ying Lee
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L21/8234
摘要： The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
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公开(公告)号：US20200075718A1
公开(公告)日：2020-03-05
申请号：US16598275
申请日：2019-10-10
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/775 , H01L29/423 , H01L29/10 , H01L29/08
摘要： The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
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公开(公告)号：US11699739B2
公开(公告)日：2023-07-11
申请号：US17586083
申请日：2022-01-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , NATIONAL TAIWAN UNIVERSITY , NATIONAL TAIWAN NORMAL UNIVERSITY
发明人： Tung-Ying Lee , Tse-An Chen , Tzu-Chung Wang , Miin-Jang Chen , Yu-Tung Yin , Meng-Chien Yang
IPC分类号： H01L29/66 , H01L21/28 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/78 , H01L21/02
CPC分类号： H01L29/6653 , H01L21/02603 , H01L21/28141 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/7851 , H01L29/78696
摘要： A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.
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公开(公告)号：US20220302315A1
公开(公告)日：2022-09-22
申请号：US17836852
申请日：2022-06-09
发明人： Feng Yuan , Ming-Shiang Lin , Chia-Cheng Ho , Jin Cai , Tzu-Chung Wang , Tung Ying Lee
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L21/8234
摘要： The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
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公开(公告)号：US11043578B2
公开(公告)日：2021-06-22
申请号：US16118143
申请日：2018-08-30
IPC分类号： H01L29/76 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/775 , H01L21/8238 , H01L21/02 , H01L21/8234
摘要： The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
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公开(公告)号：US20200273996A1
公开(公告)日：2020-08-27
申请号：US16874526
申请日：2020-05-14
发明人： Feng Yuan , Ming-Shiang Lin , Chia-Cheng Ho , Jin Cai , Tzu-Chung Wang , Tung Ying Lee
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L21/8234
摘要： The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
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