公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/40 ,  H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US20240363463A1

公开(公告)日：2024-10-31

申请号：US18766996

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US12080615B2

公开(公告)日：2024-09-03

申请号：US18068010

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2224/94 ,  H01L2224/214 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2224/19 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US12002799B2

公开(公告)日：2024-06-04

申请号：US17814766

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Yi Kuo ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Yuan Yu ,  Ming Hung Tseng

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

公开(公告)号：US11854986B2

公开(公告)日：2023-12-26

申请号：US17809961

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei-Kang Hsieh ,  Shih-Wei Chen ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/40 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L21/56 ,  H01L23/367

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/31 ,  H01L23/367 ,  H01L23/4006 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

公开(公告)号：US20230369303A1

公开(公告)日：2023-11-16

申请号：US18357457

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/73 ,  H01L23/4012 ,  H01L23/3107 ,  H01L2924/1434 ,  H01L2023/4087 ,  H01L2224/25171 ,  H01L2224/24147 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US20230369254A1

公开(公告)日：2023-11-16

申请号：US18359273

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/64 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/6835 ,  H01L21/4853 ,  H01L23/5386 ,  H01L21/4857 ,  H01L24/20 ,  H01L23/5389 ,  H01L23/3128 ,  H01L21/565 ,  H01L23/5383 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2221/68372 ,  H01L2924/1903 ,  H01L2924/1437

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

公开(公告)号：US11798925B2

公开(公告)日：2023-10-24

申请号：US17396993

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4012 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L2023/4087 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US20230245939A1

公开(公告)日：2023-08-03

申请号：US18297927

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L23/16 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US20230114652A1

公开(公告)日：2023-04-13

申请号：US18064713

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.