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公开(公告)号：US20230307375A1
公开(公告)日：2023-09-28
申请号：US18151583
申请日：2023-01-09
发明人： Hao-Cheng Hou , Tsung-Ding Wang , Jung Wei Cheng , Yu-Min Liang , Chien-Hsun Lee , Shang-Yun Hou , Wei-Yu Chen , Collin Jordon Fleshman , Kuo-Lung Pan , Shu-Rong Chun , Sheng-Chi Lin
IPC分类号： H01L23/538 , H01L23/31 , H01L23/00 , H01L25/00 , H10B80/00 , H01L25/18 , H01L21/56 , H01L23/48
CPC分类号： H01L23/5385 , H01L23/3121 , H01L24/19 , H01L24/20 , H01L25/50 , H10B80/00 , H01L25/18 , H01L21/561 , H01L23/481 , H01L23/562 , H01L2224/16227 , H01L24/16 , H01L24/29 , H01L2224/2929 , H01L2924/0665 , H01L2224/29386 , H01L2924/05442 , H01L2924/05432 , H01L2924/0503 , H01L24/32 , H01L2224/32225 , H01L24/73 , H01L2224/73204 , H01L2224/19 , H01L2224/211
摘要： A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.
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公开(公告)号：US20230053190A1
公开(公告)日：2023-02-16
申请号：US17977301
申请日：2022-10-31
发明人： Chi-Hui Lai , Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/498 , H01L23/538 , H01L21/56 , H01L23/31 , H01L23/00 , H01L21/48
摘要： In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
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公开(公告)号：US20220336410A1
公开(公告)日：2022-10-20
申请号：US17809934
申请日：2022-06-30
发明人： Chen-Hua Yu , Kuo Lung Pan , Shu-Rong Chun , Chi-Hui Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498 , H01L25/00 , H01L23/64 , H01L21/56 , H01L25/065 , H01L23/367
摘要： A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.
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公开(公告)号：US20210233835A1
公开(公告)日：2021-07-29
申请号：US17227608
申请日：2021-04-12
发明人： Chi-Hui Lai , Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/498 , H01L23/538 , H01L21/56 , H01L23/31 , H01L23/00 , H01L21/48
摘要： In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
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公开(公告)号：US11004827B2
公开(公告)日：2021-05-11
申请号：US16133702
申请日：2018-09-18
发明人： Wei Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo Lung Pan , Tin-Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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公开(公告)号：US11488897B2
公开(公告)日：2022-11-01
申请号：US17227608
申请日：2021-04-12
发明人： Chi-Hui Lai , Shu-Rong Chun , Kuo Lung Pan , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/498 , H01L21/56 , H01L23/538 , H01L23/31 , H01L23/00 , H01L21/48
摘要： In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
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公开(公告)号：US20210391270A1
公开(公告)日：2021-12-16
申请号：US17461061
申请日：2021-08-30
发明人： Shu-Rong Chun , Tin-Hao Kuo , Chi-Hui Lai , Kuo Lung Pan , Yu-Chia Lai , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/538 , H01L23/31 , H01L21/683 , H01L21/48 , H01L21/56
摘要： A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.
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公开(公告)号：US11804443B2
公开(公告)日：2023-10-31
申请号：US17461061
申请日：2021-08-30
发明人： Shu-Rong Chun , Tin-Hao Kuo , Chi-Hui Lai , Kuo Lung Pan , Yu-Chia Lai , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L23/538 , H01L23/31 , H01L21/683 , H01L21/48 , H01L21/56
CPC分类号： H01L23/5386 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/5383 , H01L2221/68372
摘要： A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.
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公开(公告)号：US20200091114A1
公开(公告)日：2020-03-19
申请号：US16133702
申请日：2018-09-18
发明人： Wei Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo Lung Pan , Tin-Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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