公开(公告)号：US20110037175A1

公开(公告)日：2011-02-17

申请号：US12540759

申请日：2009-08-13

Applicant: Sarunya Bangsaruntip ,  Daniel C. Edelstein ,  William D. Hinsberg ,  Ho-Cheol Kim ,  Steven Koester ,  Paul M. Solomon

Inventor： Sarunya Bangsaruntip ,  Daniel C. Edelstein ,  William D. Hinsberg ,  Ho-Cheol Kim ,  Steven Koester ,  Paul M. Solomon

IPC: H01L23/48 ,  H05K1/11 ,  B05D5/12 ,  G03F7/20

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.

Abstract translation: 形成了亚光刻间距结构和光刻凸出结构之间的互连。 具有亚光刻间距的多条导线可以被光刻图案化并且沿着与多根导线的长度方向成小于45度的角度的切割。 或者，与均聚物混合的共聚物可以放置在凹陷区域中并自对准以形成在恒定宽度区域具有亚光刻间距的多条导线，以及在梯形区域处的相邻线之间的光刻尺寸。 或者，具有亚光刻间距的第一多个导线和具有光刻间距的第二多个导线可以形成在相同的水平或不同的位置。

公开(公告)号：US20080001173A1

公开(公告)日：2008-01-03

申请号：US11767188

申请日：2007-06-22

Applicant: Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi ,  Yanning Sun

Inventor： Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  Ghavam Shahidi ,  Yanning Sun

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

公开(公告)号：US20050023554A1

公开(公告)日：2005-02-03

申请号：US10883434

申请日：2004-07-01

Applicant: Jack Chu ,  Khalid Ismail ,  Steven Koester ,  Bernd-Ulrich Klepser

Inventor： Jack Chu ,  Khalid Ismail ,  Steven Koester ,  Bernd-Ulrich Klepser

IPC: H01L31/10 ,  H01L27/144 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/072

CPC classification number: B82Y20/00 ,  H01L27/1443 ,  H01L31/0312 ,  H01L31/035254

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract translation: 描述了一种集成的光电子电路和制造工艺，其中结合了光电探测器和芯片上的MODFET。 该芯片包含单晶半导体衬底，组成SiGe缓冲层，弛豫SiGe层，量子阱层，未掺杂的SiGe间隔层和掺杂的SiGe供应层。 光电检测器可以是金属 - 半导体 - 金属（MSM）或p-i-n器件。 检测器可以与n型或p型MODFET集成，或者以CMOS配置集成，并且该MODFET可以并入肖特基或绝缘栅。 本发明克服了通过使用表面生长的Si / SiGe异质结构层制造用于850nm工作的Si制造兼容的单片高速光电子电路的问题。

公开(公告)号：US07989900B2

公开(公告)日：2011-08-02

申请号：US12544452

申请日：2009-08-20

Applicant: Wilfried Haensch ,  Steven Koester ,  Amlan Majumdat

Inventor： Wilfried Haensch ,  Steven Koester ,  Amlan Majumdat

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L21/26586 ,  H01L21/28026 ,  H01L21/28105 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/4232 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device.

Abstract translation: 诸如CMOS结构的半导体结构包括具有横向可变功函数的栅电极。 具有横向可变功函数的栅电极可以使用成角度离子注入法或顺序分层方法形成。 具有横向可变功函数的栅电极在未掺杂的沟道场效应晶体管器件内提供增强的电性能。

公开(公告)号：US20050077510A1

公开(公告)日：2005-04-14

申请号：US10685013

申请日：2003-10-14

Applicant: Jack Chu ,  Steven Koester ,  Qiqing Ouyang

Inventor： Jack Chu ,  Steven Koester ,  Qiqing Ouyang

IPC: H01L29/06 ,  H01L21/20 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812 ,  H01L31/0328 ,  H01L21/336

CPC classification number: H01L29/66431 ,  H01L29/7782 ,  Y10S438/933 ,  Y10S438/938

Abstract: A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects. The MODFET design includes a high-mobility conducting channel layer wherein the method allows the counter doping to be formed using a standard technique such as ion implantation, and further allows the high-mobility channel to be in close proximity to the counter doping without degradation of the mobility.

Abstract translation: 制造高迁移率半导体层结构的结构和方法以及包括高迁移率导电沟道的场效应晶体管（MODFET），同时保持反掺杂以控制有害的短沟道效应。 MODFET设计包括高迁移率导电沟道层，其中该方法允许使用诸如离子注入的标准技术形成反相掺杂，并且还允许高迁移率通道紧邻反掺杂而不降解 流动性。

公开(公告)号：US08263477B2

公开(公告)日：2012-09-11

申请号：US12684331

申请日：2010-01-08

Applicant: Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

Inventor： Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/7391 ,  H01L21/2007 ,  H01L21/76254 ,  H01L29/66227

Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.

Abstract translation: 制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

公开(公告)号：US20110220805A1

公开(公告)日：2011-09-15

申请号：US12719962

申请日：2010-03-09

Applicant: Michael Gordon ,  Steven Koester ,  Kenneth Rodbell ,  Jeng-Bang Yau

Inventor： Michael Gordon ,  Steven Koester ,  Kenneth Rodbell ,  Jeng-Bang Yau

IPC: G01T1/24 ,  H01L31/08

CPC classification number: H01L31/119

Abstract: A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. A method for radiation monitoring, the method includes applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.

Abstract translation: 半导体器件包括半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。 一种用于辐射监测的方法，所述方法包括将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。

公开(公告)号：US20110169051A1

公开(公告)日：2011-07-14

申请号：US12684331

申请日：2010-01-08

Applicant: Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

Inventor： Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/7391 ,  H01L21/2007 ,  H01L21/76254 ,  H01L29/66227

Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.

Abstract translation: 制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。

公开(公告)号：US20080197424A1

公开(公告)日：2008-08-21

申请号：US11677207

申请日：2007-02-21

Applicant: Wilfried Haensch ,  Steven Koester ,  Amlan Majumdar

Inventor： Wilfried Haensch ,  Steven Koester ,  Amlan Majumdar

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66772 ,  H01L21/26586 ,  H01L21/28026 ,  H01L21/28105 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/4232 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device.

Abstract translation: 诸如CMOS结构的半导体结构包括具有横向可变功函数的栅电极。 具有横向可变功函数的栅电极可以使用成角度离子注入法或顺序分层方法形成。 具有横向可变功函数的栅电极在未掺杂的沟道场效应晶体管器件内提供增强的电性能。

公开(公告)号：US20070093074A1

公开(公告)日：2007-04-26

申请号：US11259165

申请日：2005-10-26

Applicant: Martin Frank ,  Steven Koester ,  John Ott ,  Huiling Shang

Inventor： Martin Frank ,  Steven Koester ,  John Ott ,  Huiling Shang

IPC: H01L21/31

CPC classification number: H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

Abstract: A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

Abstract translation: 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长期间和之后不期望的界面化合物的形成，并且界面陷阱的密度降低。