公开(公告)号：USD630667S1

公开(公告)日：2011-01-11

申请号：US29344516

申请日：2009-09-30

Applicant: Shinro Inui ,  Tatsuo Morita

Designer： Shinro Inui ,  Tatsuo Morita

公开(公告)号：US08248042B2

公开(公告)日：2012-08-21

申请号：US13336621

申请日：2011-12-23

Applicant: Tatsuo Morita

Inventor： Tatsuo Morita

IPC: G05F1/00 ,  H02M7/5387

CPC classification number: H01L29/7787 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/423 ,  H01L29/432 ,  H02M7/003 ,  Y02B70/1483

Abstract: A power converter includes an input terminal configured to be connected to a power supply, an output terminal, and a first switching element coupled between the input terminal and the output terminal. The first switching element includes a semiconductor multilayer structure formed on a substrate and made of a nitride semiconductor, a gate electrode formed on the semiconductor multilayer structure, a first and a second ohmic electrode, and a back electrode formed on a back surface of the substrate. A potential is supplied from the power supply connected to the input terminal to the back electrode so that a potential difference between the back surface and the second ohmic electrode is reduced. When the first switching element is in the on-state, a positive voltage bias is applied to the back electrode.

Abstract translation: 功率转换器包括被配置为连接到电源，输出端子和耦合在输入端子和输出端子之间的第一开关元件的输入端子。 第一开关元件包括形成在衬底上并由氮化物半导体形成的半导体多层结构，形成在半导体多层结构上的栅电极，第一和第二欧姆电极以及形成在衬底的背面上的背电极 。 从连接到输入端子的电源向背面电极提供电位，使得背面与第二欧姆电极之间的电位差减小。 当第一开关元件处于导通状态时，正电压偏压被施加到背电极。

公开(公告)号：US20100207164A1

公开(公告)日：2010-08-19

申请号：US12682007

申请日：2009-08-07

Applicant: Daisuke Shibata ,  Tatsuo Morita ,  Yasuhiro Uemoto

Inventor： Daisuke Shibata ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC: H01L29/772

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766

Abstract: A field effect transistor includes a first nitride semiconductor layer 13 and a second nitride semiconductor layer 14 having a band gap larger than that of the first nitride semiconductor layer 13 which are formed in this order in an upward direction on a conductive substrate 11, a source electrode 15 and a drain electrode 16 which are electrically connected to a two-dimensional electron gas layer 21, and a gate electrode 18. A rise voltage of a drain-substrate current is lower than a rise voltage of a drain-gate current and a rise voltage of a drain-source current.

Abstract translation: 场效应晶体管包括第一氮化物半导体层13和具有大于第一氮化物半导体层13的带隙的第二氮化物半导体层14，该第二氮化物半导体层14在导电基板11上沿向上方向依次形成，源极 与二维电子气体层21电连接的电极15和漏电极16以及栅极电极18.漏极 - 基板电流的上升电压低于漏极 - 栅极电流的上升电压，并且 漏 - 源电流的上升电压。

公开(公告)号：US07728359B2

公开(公告)日：2010-06-01

申请号：US11812591

申请日：2007-06-20

Applicant: Tatsuo Morita ,  Tetsuzo Ueda

Inventor： Tatsuo Morita ,  Tetsuzo Ueda

IPC: H01L51/00

CPC classification number: H01L29/2003 ,  H01L29/201 ,  H01L29/66318 ,  H01L29/7371

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract translation: 在基于氮化物半导体的双极型晶体管中，形成为与发射极层接触的接触层由n型InAlGaN四元混晶构成，选择性地去除发射极层和接触层，使得其上形成有发射极的势垒高度 例如，在InAlGaN四元混晶中的欧姆电极接触电阻可以降低，使得WSi发射极成为檐。 通过使用发射电极作为掩模的自对准工艺形成基极。 通过这样的结构，能够充分地缩短发射极与基极的边缘之间的距离，能够降低基极电阻。 结果，可以实现具有良好的高频特性的双极晶体管。

公开(公告)号：US07465968B2

公开(公告)日：2008-12-16

申请号：US11600067

申请日：2006-11-16

Applicant: Tetsuzo Ueda ,  Satoshi Nakazawa ,  Tatsuo Morita

Inventor： Tetsuzo Ueda ,  Satoshi Nakazawa ,  Tatsuo Morita

IPC: H01L29/737

CPC classification number: H01L29/452 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/8122

Abstract: A semiconductor device includes: a first nitride semiconductor layer having at least one projection on an upper surface thereof; a second nitride semiconductor layer formed on a top surface of the projection of the first nitride semiconductor layer and having a higher carrier concentration than the first nitride semiconductor layer; a first electrode formed on the second nitride semiconductor layer so as to overhang like a canopy and functioning as one of a source and a drain; and a second electrode formed to the side of the projection on the first nitride semiconductor layer and functioning as a gate.

Abstract translation: 半导体器件包括：在其上表面上具有至少一个突起的第一氮化物半导体层; 第二氮化物半导体层，其形成在所述第一氮化物半导体层的所述突起的顶表面上，并且具有比所述第一氮化物半导体层更高的载流子浓度; 第一电极，形成在第二氮化物半导体层上，以便像顶盖一样悬垂并用作源极和漏极之一; 以及第二电极，其形成在第一氮化物半导体层上的突起侧并用作栅极。

公开(公告)号：US07364327B2

公开(公告)日：2008-04-29

申请号：US11822588

申请日：2007-07-09

Applicant: Takeshi Katayama ,  Hideharu Saito ,  Keiichiro Tokushige ,  Tatsuo Morita

Inventor： Takeshi Katayama ,  Hideharu Saito ,  Keiichiro Tokushige ,  Tatsuo Morita

IPC: F21V29/00

CPC classification number: F21V15/01 ,  G02F1/13 ,  G02F1/1333 ,  G03B21/00 ,  G03B21/16

Abstract: Reduction of noise is achieved by devising an arrangement of heat generating parts such as a light valve element, an electric power source, a light source, etc. and an arrangement of cooling fans. In cooling the light source, the electric power source and liquid crystal panels, a cooling wind path for the liquid crystal panels and the electric power source is made separate from and independent of a cooling wind path for the light source that generates much heat, a cooling air volume is optimized for the respective cooling wind paths, and noise accompanying the rotation of the cooling fans is reduced. Also, by arranging the cooling fans substantially centrally of the respective cooling wind paths, that volume of noise, which leaks from air intake ports and air exhaust port that are opened to a housing of a unit, is reduced.

Abstract translation: 通过设计诸如光阀元件，电源，光源等的发热部件的布置和冷却风扇的布置来实现噪声的降低。 在冷却光源时，电源和液晶面板，用于液晶面板和电源的冷却风路被分离并且独立于产生大量热量的光源的冷却风路， 针对相应的冷却风路优化了冷却风量，并且降低伴随着冷却风扇旋转的噪音。 此外，通过将冷却风扇基本上布置在相应的冷却风路的中央，减小了从对单元的壳体开放的进气口和排气口泄漏的噪声的体积。

公开(公告)号：US20070131968A1

公开(公告)日：2007-06-14

申请号：US11603224

申请日：2006-11-22

Applicant: Tatsuo Morita ,  Tetsuzo Ueda

Inventor： Tatsuo Morita ,  Tetsuzo Ueda

IPC: H01L31/00

CPC classification number: H01L21/28581 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7786

Abstract: A material of a gate electrode is a conductive oxide having a higher work function than that of conventionally used Pd and so on, thereby achieving a normally-off transistor without reducing the sheet carrier concentration of a heterojunction. It is thus possible to achieve a normally-off operation while reducing an increase in the specific on-state resistance.

Abstract translation: 栅电极的材料是具有比常规使用的Pd等功函数高的导电氧化物，从而在不降低异质结的片载体浓度的情况下实现常关晶体管。 因此，可以在减小特定导通电阻的增加的同时实现常关断操作。

公开(公告)号：US06991335B2

公开(公告)日：2006-01-31

申请号：US10817001

申请日：2004-04-05

Applicant: Yoshihiro Kondo ,  Nariaki Shigyo ,  Katsunori Nakatani ,  Tatsuo Morita

Inventor： Yoshihiro Kondo ,  Nariaki Shigyo ,  Katsunori Nakatani ,  Tatsuo Morita

IPC: G03B21/14 ,  G03B21/18 ,  G03B21/22

CPC classification number: H04N5/7441 ,  G03B21/16 ,  H04N9/3141

Abstract: In order to perform high efficient cooling without boiling cooling liquid and to improve maintainability such as replacement of a lamp, the present invention provides a liquid crystal projector including a light source lamp, a liquid crystal panel, a power source, a fan for removing heat generated by the power source and the lamp, a water-cooling jacket provided on an inner surface of an external wall portion opposed to the lamp in the liquid crystal projector, a metal pipe arrangement for radiation which is placed in the external wall portion, and a pump for driving cooling liquid to flow in the water-cooling jacket so that the cooling liquid receiving the heat from the lamp circulates in a circulation path through the water-cooling jacket, the metal pipe arrangement, and the pump to emit the heat to the outside through the metal pipe arrangement.

Abstract translation: 为了在没有沸腾冷却液的情况下进行高效冷却，并且为了提高灯的更换等维护性，本发明提供一种液晶投影机，其包括光源灯，液晶面板，电源，除热用的风扇 由电源和灯产生的水冷套，设置在与液晶投影仪中的灯相对的外壁部分的内表面上的水冷套管，放置在外壁部分中的用于辐射的金属管装置，以及 用于驱动冷却液体在水冷套中流动的泵，使得从灯中接收热量的冷却液在循环路径中循环通过水冷套管，金属管装置和泵，以将热量发射到 外部通过金属管道排列。

公开(公告)号：US5982348A

公开(公告)日：1999-11-09

申请号：US921839

申请日：1997-09-02

Applicant: Setsuo Nakajima ,  Katunobu Awane ,  Tatsuo Morita

Inventor： Setsuo Nakajima ,  Katunobu Awane ,  Tatsuo Morita

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L29/78 ,  H01L29/786

CPC classification number: G02F1/13454 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2320/0219 ,  H01L27/1214

Abstract: In an active matrix display device integrated with a peripheral drive circuit using thin film transistors, when Vgr is a voltage required for one gradation, Ct is capacitance of all pixels, Cgd is capacitance between a gate and a drain, .DELTA.Vg is a difference between ON/OFF gate voltages, and .DELTA.Vs is a feedthrough voltage, the respective parameters satisfy an expression: .vertline.vgr.vertline.>.vertline.(1/Ct)[Cgd.multidot..DELTA.Vg-Ct.multidot..DELTA.Vs].vertline.. According to this, even if dispersion occurs in the characteristics of the thin film transistors arranged for a buffer circuit or an active matrix circuit, it is possible to prevent the dispersion from influencing the gradation display.

Abstract translation: 在与使用薄膜晶体管的外围驱动电路集成的有源矩阵显示装置中，当Vgr是一个灰度所需的电压时，Ct是所有像素的电容，Cgd是栅极和漏极之间的电容，DELTA Vg是 ON / OFF栅极电压和DELTA Vs是馈通电压，各个参数满足表达式：| vgr |> |（1 / Ct）[Cgdx DELTA Vg-Ctx DELTA Vs] |。 据此，即使在布置用于缓冲电路或有源矩阵电路的薄膜晶体管的特性中发生色散，也可以防止色散影响灰度显示。

公开(公告)号：US4930477A

公开(公告)日：1990-06-05

申请号：US258685

申请日：1988-10-17

Applicant: Yasutoshi Nanyoshi ,  Toshio Matsumura ,  Tatsuo Morita ,  Hidetoshi Shigyo

Inventor： Yasutoshi Nanyoshi ,  Toshio Matsumura ,  Tatsuo Morita ,  Hidetoshi Shigyo

IPC: F02P5/15

CPC classification number: F02P5/1504 ,  Y02T10/46

Abstract: A system and method for controlling an ignition timing for an internal combustion engine mounted in a vehicle are disclosed in which a limit value for the ignition timing value is provided so that a difference between a current ignition timing and a previous ignition timing is within the limit value and the limit value is set according to a magnitude of an engine acceleration. For example, when an abrupt engine acceleration occurs, the limit value is set to 15 degrees. When the engine is in a steady state (no abrupt acceleration from an idling condition), the limit value is set to four degrees. Therefore, no vehicle body shock occurs due to the abrupt change in an engine output torque caused by the abrupt change in the ignition timing and a response characteristic of a rise in the engine output torque during the abrupt acceleration can be assured.

Abstract translation: 公开了一种用于控制安装在车辆中的内燃机的点火正时的系统和方法，其中提供了点火正时值的极限值，使得当前点火正时与先前点火正时之间的差值在极限内 值，并且根据发动机加速度的大小设定极限值。 例如，当发生急剧的发动机加速时，将极限值设定为15度。 当发动机处于稳定状态（没有从怠速状态突然加速）时，极限值设定为4度。 因此，由于点火正时突然变化引起的发动机输出转矩突然变化，并且可以确保突发加速期间的发动机输出转矩的上升的响应特性，所以不会发生车身冲击。