公开(公告)号：US4078401A

公开(公告)日：1978-03-14

申请号：US799279

申请日：1977-05-23

Applicant: Shigeo Kamikura ,  Yutaka Kagaya ,  Kensuke Uemura

Inventor： Shigeo Kamikura ,  Yutaka Kagaya ,  Kensuke Uemura

IPC: D04B15/78 ,  D04B7/08 ,  D04B15/66 ,  D04B7/00

CPC classification number: D04B15/66

Abstract: A method and apparatus for providing patterning instructions in a knitting machine by reading a program carrier and converting the readings to digital signals to be stored in a memory means. A manually operable member cooperating with the reading means allows the instructions to be recalled from memory to be selectively determined for controlling for the knitting operation.

Abstract translation: 一种用于通过读取程序载体并将读数转换成存储在存储装置中的数字信号在针织机中提供图案化指令的方法和装置。 与读取装置协作的可手动操作的构件允许从存储器调用指令以选择性地确定用于编织操作的控制。

公开(公告)号：US4085597A

公开(公告)日：1978-04-25

申请号：US737433

申请日：1976-11-01

Applicant: Shigeo Kamikura ,  Hideaki Itagaki ,  Yutaka Kagaya ,  Ryoiti Kawaoka

Inventor： Shigeo Kamikura ,  Hideaki Itagaki ,  Yutaka Kagaya ,  Ryoiti Kawaoka

IPC: D04B15/66 ,  D04B7/00

CPC classification number: D04B15/66

Abstract: A new type of hand-operated knitting machine having a device for reading knitting programs is provided. Unlike the conventional reading device-equipped knitting machine, the reading device is not mounted on its carriage. Therefore, although the scanning operation of the reading device is associated with the start of the carriage movement, it is not disordered by irregular carriage handlings, thus realizing proper reproduction of the knitting pattern.

Abstract translation: 提供了一种具有用于读取编织程序的装置的新型手动编织机。 与传统的装备有读取装置的针织机不同，读取装置不安装在其托架上。 因此，尽管读取装置的扫描操作与托架运动的开始相关联，但是它不会由于不规则的托架处理而无序，从而实现编织图案的适当再现。

公开(公告)号：US08247896B2

公开(公告)日：2012-08-21

申请号：US12875799

申请日：2010-09-03

Applicant: Yutaka Kagaya ,  Hidehiro Takeshima ,  Masamichi Ishihara

Inventor： Yutaka Kagaya ,  Hidehiro Takeshima ,  Masamichi Ishihara

IPC: H01L23/02

CPC classification number: H01L24/97 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.

Abstract translation: 叠层半导体器件通过两层叠层构成：具有布线板的下半导体器件，安装在布线板的第一表面上的至少一个半导体芯片，并且具有通过连接装置电连接到布线的电极， 由覆盖半导体芯片的绝缘塑料和连接装置构成的密封剂，形成在布线板的第二表面的布线上的多个电极，以及多个连接互连，每个连接互连具有连接到第一表面的布线的部分 的布线板，另一部分露出在密封剂的表面上; 以及上半导体器件，其中每个电极覆盖并电连接到下半导体器件的每个连接互连的暴露部分。 连接互连从布线板的第一表面延伸到密封剂的侧表面和上表面，此外，与从密封剂突出的布线板的布线电连接。

公开(公告)号：US20050258519A1

公开(公告)日：2005-11-24

申请号：US10921961

申请日：2004-08-20

Applicant: Koya Kikuchi ,  Noriou Shimada ,  Keiyo Kusanagi ,  Akihiko Hatasawa ,  Yutaka Kagaya

Inventor： Koya Kikuchi ,  Noriou Shimada ,  Keiyo Kusanagi ,  Akihiko Hatasawa ,  Yutaka Kagaya

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/16 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/52

CPC classification number: H01L24/50 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract translation: 半导体器件包括：具有器件孔和多个孔的绝缘带; 多个引线形成在带的一个表面上并且在一端延伸到器件孔中并在另一端延伸到孔中; 在其主表面上具有多个电极的半导体芯片与延伸到器件孔中的引线连接; 由绝缘树脂形成的密封剂，引线和带的预定部分; 设置在引线的一个表面上的凸起电极; 设置在密封剂和凸起电极之间的带中的狭缝，并且沿凸起电极的一列延伸; 以及由绝缘膜制成并形成在所述带上的防扭曲加强件; 其中半导体芯片和凸块电极连接到引线的同一表面侧。

公开(公告)号：US06452266B1

公开(公告)日：2002-09-17

申请号：US10024011

申请日：2001-12-21

Applicant: Akihiko Iwaya ,  Toshio Sugano ,  Susumu Hatano ,  Yutaka Kagaya ,  Masachika Masuda

Inventor： Akihiko Iwaya ,  Toshio Sugano ,  Susumu Hatano ,  Yutaka Kagaya ,  Masachika Masuda

IPC: H01L2144

CPC classification number: H01L21/563 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15151 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2. Each chip 1 has a plurality of pads 9 which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads 9a that are located on the side of central part on a specified plane of the substrate 2, and control-use pads 9b of control signals that are also placed on the center side of the substrate 2. The pad array also includes input/output pads 9c that are disposed so that these are on the peripheral side on the surface of substrate 2.

公开(公告)号：US08524890B2

公开(公告)日：2013-09-03

申请号：US13138426

申请日：2010-02-24

Applicant: Hiroaki Isago ,  Yutaka Kagaya ,  Youichi Oyama ,  Harumi Fujita

Inventor： Hiroaki Isago ,  Yutaka Kagaya ,  Youichi Oyama ,  Harumi Fujita

IPC: C09B47/04

CPC classification number: C09B47/08 ,  A61K41/0071 ,  C09D11/328

Abstract: The invention has for its object to provide a water-soluble phthalocyanine dye unlikely to lose its own properties even upon dissolved in a concentration as high as 10−5 M.The inventive water-soluble phthalocyanine dye is characterized by having a sulfuric acid group or groups as an axial ligand or ligands of an antimony/phthalocyanine complex. The sulfuric acid group or groups have been introduced by replacing a part or the whole of hydroxyl groups in the starting material with a sulfuric acid group or groups.

Abstract translation: 本发明的目的是提供即使溶于高达10-5M的浓度也不会失去其自身特性的水溶性酞菁染料。本发明的水溶性酞菁染料的特征在于具有硫酸基或 基团作为锑/酞菁络合物的轴配体或配体。 通过用硫酸基团代替起始原料中的一部分或全部羟基，引入硫酸基团。

公开(公告)号：US20080199979A1

公开(公告)日：2008-08-21

申请号：US12104774

申请日：2008-04-17

Applicant: Koya KIKUCHI ,  Noriou Shimada ,  Keiyo Kusanagi ,  Akihiko Hatasawa ,  Yutaka Kagaya

Inventor： Koya KIKUCHI ,  Noriou Shimada ,  Keiyo Kusanagi ,  Akihiko Hatasawa ,  Yutaka Kagaya

IPC: H01L21/66

CPC classification number: H01L24/50 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/86 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/351 ,  H01L2924/00

Abstract: Method of manufacturing a semiconductor device, including: preparing a TAB tape featuring an insulating tape having a device hole and a plurality of holes, a plurality of leads formed on a surface of the tape and extending at one end into the device hole and at the other end into the holes, slits provided inside arrangements of columns of holes, and a warp prevention reinforcement insulating film to hold the leads between it and the tape; connecting front ends of the leads to the electrodes of the chip; forming an encapsulant to enclose the chip, the leads and a portion of the tape; forming thick bump electrodes on that surface side of the leads running through the holes to which the semiconductor chip is connected; performing an electric characteristic test, using the bump electrodes as measuring terminals; and cutting the TAB tape to a predetermined shape.

Abstract translation: 一种制造半导体器件的方法，包括：制备具有绝缘带的TAB带，该绝缘带具有器件孔和多个孔，多个引线形成在带的表面上并且在一端延伸到器件孔中 设置在孔的内部布置中的狭缝，以及将引线保持在带之间的防翘曲加强绝缘膜; 将引线的前端连接到芯片的电极; 形成密封剂以包围芯片，引线和磁带的一部分; 在穿过与半导体芯片连接的孔的引线的表面侧上形成厚的凸起电极; 使用凸块电极作为测量端子进行电特性测试; 并将TAB带切割成预定的形状。

公开(公告)号：US20070241437A1

公开(公告)日：2007-10-18

申请号：US11734054

申请日：2007-04-11

Applicant: Yutaka Kagaya ,  Hidehiro Takeshima ,  Masamichi Ishihara

Inventor： Yutaka Kagaya ,  Hidehiro Takeshima ,  Masamichi Ishihara

IPC: H01L23/02

CPC classification number: H01L24/97 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.

Abstract translation: 叠层半导体器件通过两层叠层构成：具有布线板的下半导体器件，安装在布线板的第一表面上的至少一个半导体芯片，并且具有通过连接装置电连接到布线的电极， 由覆盖半导体芯片的绝缘塑料和连接装置构成的密封剂，形成在布线板的第二表面的布线上的多个电极，以及多个连接互连，每个连接互连具有连接到第一表面的布线的部分 的布线板，另一部分露出在密封剂的表面上; 以及上半导体器件，其中每个电极覆盖并电连接到下半导体器件的每个连接互连的暴露部分。 连接互连从布线板的第一表面延伸到密封剂的侧表面和上表面，此外，与从密封剂突出的布线板的布线电连接。

公开(公告)号：US06617196B2

公开(公告)日：2003-09-09

申请号：US10024364

申请日：2001-12-21

Applicant: Akihiko Iwaya ,  Toshio Sugano ,  Susumu Hatano ,  Yutaka Kagaya ,  Masachika Masuda

Inventor： Akihiko Iwaya ,  Toshio Sugano ,  Susumu Hatano ,  Yutaka Kagaya ,  Masachika Masuda

IPC: H01L2144

CPC classification number: H01L21/563 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15151 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2. Each chip 1 has a plurality of pads 9 which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads 9a that are located on the side of central part on a specified plane of the substrate 2, and control-use pads 9b of control signals that are also placed on the center side of the substrate 2. The pad array also includes input/output pads 9c that are disposed so that these are on the peripheral side on the surface of substrate 2.

公开(公告)号：US4105157A

公开(公告)日：1978-08-08

申请号：US821811

申请日：1977-08-04

Applicant: Yutaka Kagaya

Inventor： Yutaka Kagaya

IPC: D04B15/86 ,  D04B20060101 ,  D04B15/66 ,  G05B19/12 ,  G06K20060101 ,  G06K7/015 ,  G06K13/00 ,  D03D49/00 ,  G06K7/10

CPC classification number: G06K7/015 ,  D04B15/66 ,  G05B19/12

Abstract: A program reading apparatus in a knitting machine including a movable reading head adapted to scan a program carrier having thereon patterning instructions for control of the pattern to be knitted on the machine. Means are provided therein for preventing rebound of the reading head upon arrival at or return to its starting position, such means being operated by the momentum of the reading head upon reading head arrival or return to momentarily arrest the reading head at the starting position.

Abstract translation: 一种编织机中的程序读取装置，包括：可移动读取头，用于扫描具有用于控制在机器上编织的图案的图案化指令的程序载体。 在其中设置有用于在到达或返回其起始位置时防止读取头反弹的装置，这种装置在读取头到达时返回到读取头的动量或者在开始位置暂时停止读取头。