Invention Grant
- Patent Title: Stacked semiconductor device and fabrication method for same
- Patent Title (中): 堆叠的半导体器件及其制造方法相同
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Application No.: US12875799Application Date: 2010-09-03
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Publication No.: US08247896B2Publication Date: 2012-08-21
- Inventor: Yutaka Kagaya , Hidehiro Takeshima , Masamichi Ishihara
- Applicant: Yutaka Kagaya , Hidehiro Takeshima , Masamichi Ishihara
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2006-113529 20060417
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.
Public/Granted literature
- US20110001235A1 STACKED SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME Public/Granted day:2011-01-06
Information query
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