公开(公告)号：US08828795B2

公开(公告)日：2014-09-09

申请号：US13616618

申请日：2012-09-14

申请人： Sang-Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

发明人： Sang-Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

IPC分类号： H01L21/60 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

摘要翻译： 一种半导体封装，包括基底基板，安装在基底基板上的半导体芯片，并且包括接合焊盘，与基板上的半导体芯片相邻设置并电连接到焊盘的第一和第二连接端子， 所述基底基板电连接到所述第一连接端子，与所述连接端子间隔开的第二球形台面，设置在所述第二球形台面与所述第一和第二连接端子中的至少一个之间的所述第一球形区域， 第一球接地，但暴露第二球台的至少一部分，以及延伸到第一绝缘层上并将第二连接端子连接到第二球台的第一导线。

公开(公告)号：US20100314760A1

公开(公告)日：2010-12-16

申请号：US12794027

申请日：2010-06-04

申请人： Sang Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

发明人： Sang Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

IPC分类号： H01L23/538 ,  H01L23/488 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

摘要翻译： 一种半导体封装，包括基底基板，安装在基底基板上的半导体芯片，并且包括接合焊盘，与基板上的半导体芯片相邻设置并电连接到焊盘的第一和第二连接端子， 所述基底基板电连接到所述第一连接端子，与所述连接端子间隔开的第二球形台面，设置在所述第二球形台面与所述第一和第二连接端子中的至少一个之间的所述第一球形区域， 第一球接地，但暴露第二球台的至少一部分，以及延伸到第一绝缘层上并将第二连接端子连接到第二球台的第一导线。

公开(公告)号：US08304892B2

公开(公告)日：2012-11-06

申请号：US12794027

申请日：2010-06-04

申请人： Sang-Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

发明人： Sang-Gui Jo ,  Ji-Yong Park ,  Kwangjin Bae ,  Soyoung Lim

IPC分类号： H01L23/488

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

摘要翻译： 一种半导体封装，包括基底基板，安装在基底基板上的半导体芯片，并且包括接合焊盘，与基板上的半导体芯片相邻设置并电连接到焊盘的第一和第二连接端子， 所述基底基板电连接到所述第一连接端子，与所述连接端子间隔开的第二球形台面，设置在所述第二球形台面与所述第一和第二连接端子中的至少一个之间的所述第一球形区域， 第一球接地，但暴露第二球台的至少一部分，以及延伸到第一绝缘层上并将第二连接端子连接到第二球台的第一导线。

公开(公告)号：US08466554B2

公开(公告)日：2013-06-18

申请号：US13028836

申请日：2011-02-16

申请人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

发明人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/12 ,  H01L23/053

CPC分类号： H01L24/03 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/1403 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer.

摘要翻译： 电子设备包括形成在基板的第一表面上并彼此间隔开的第一和第二互连。 电子设备包括设置在基板上的第一绝缘材料层，包括第一和第二互连，并且包括暴露第一互连的预定区域的第一开口。 电子设备还包括填充第一开口并且具有比第一开口更大的宽度的第一垫。 第一焊盘覆盖与第一互连的一端相邻的第二互连的至少一部分，并且第一焊盘通过第一绝缘材料层与第二互连电绝缘。

公开(公告)号：US20110227221A1

公开(公告)日：2011-09-22

申请号：US13028836

申请日：2011-02-16

申请人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

发明人： Ji-Yong Park ,  Hee-Seok Lee ,  Chul-Woo Kim ,  Sang-Gui Jo ,  Kwang-Jin Bae ,  Seung-Hwan Kim

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/1403 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer.

摘要翻译： 电子设备包括形成在基板的第一表面上并彼此间隔开的第一和第二互连。 电子设备包括设置在基板上的第一绝缘材料层，包括第一和第二互连，并且包括暴露第一互连的预定区域的第一开口。 电子设备还包括填充第一开口并且具有比第一开口更大的宽度的第一垫。 第一焊盘覆盖与第一互连的一端相邻的第二互连的至少一部分，并且第一焊盘通过第一绝缘材料层与第二互连电绝缘。

公开(公告)号：US09321940B2

公开(公告)日：2016-04-26

申请号：US13995873

申请日：2011-11-21

申请人： Ji-Yong Park ,  Moon-Ki Yea ,  Jung-Eun Ha

发明人： Ji-Yong Park ,  Moon-Ki Yea ,  Jung-Eun Ha

IPC分类号： B29C65/52 ,  B32B37/02 ,  B32B37/12 ,  B32B37/28 ,  B32B38/10 ,  B32B38/12 ,  B32B38/14 ,  C09J7/02 ,  B44C1/17 ,  B44C1/10

CPC分类号： C09J7/0264 ,  B44C1/105 ,  B44C1/1729 ,  C09J7/22 ,  Y10T428/1476

摘要： The present invention relates to a decorative sheet for decorating a surface of a three-dimensional molded material, a method for manufacturing same, and a method for decorating the surface of the molded material using same. The method for manufacturing the decorative sheet includes: a printed sheet preparation step of preparing a printed sheet including a base layer and a surface treatment layer; an boding step of preparing an adhesive layer containing an adhesive and a release film layer by applying the adhesive onto a release film to be layered onto a back side of the adhesive layer, and laminating the printed sheet on a surface of the adhesive layer being bonded; and a drying-solidifying step in which the adhesive layer is changed from a liquid state into a solid state.

摘要翻译： 本发明涉及一种用于装饰三维成型材料的表面的装饰片，其制造方法，以及使用该装饰材料装饰成型材料的表面的方法。 制造装饰片的方法包括：印刷片制备步骤，制备包括基底层和表面处理层的印刷片; 通过将粘合剂施加到剥离膜上以层压到粘合剂层的背面上来制备包含粘合剂和剥离膜层的粘合剂层的粘合步骤，并且将粘合剂层粘合在粘合剂层的表面上 ; 和干燥固化步骤，其中粘合剂层从液态变为固态。

公开(公告)号：US08852853B2

公开(公告)日：2014-10-07

申请号：US13178013

申请日：2011-07-07

申请人： Ki Hoon Kim ,  Ji-Yong Park ,  Jin-Suk Park ,  Sunghyuk Kim ,  Min-Chang Kim ,  Kyung Hyun Choi

发明人： Ki Hoon Kim ,  Ji-Yong Park ,  Jin-Suk Park ,  Sunghyuk Kim ,  Min-Chang Kim ,  Kyung Hyun Choi

IPC分类号： G03F7/20 ,  G02F1/1333 ,  G03F1/54 ,  G02F1/1337 ,  G02F1/1341

CPC分类号： G02F1/133351 ,  G02F2001/133796 ,  G02F2001/13415 ,  G03F1/54

摘要： A photo-mask is capable of preventing stain defects and a method for fabricating a liquid crystal display device using the photo-mask which achieves the same capability. The photo-mask includes a transparent substrate configured to transmit ultraviolet light and a light shielding layer configured to block ultraviolet light on a surface of the transparent substrate. The light shielding layer includes an absorption layer configured to absorb ultraviolet light.

摘要翻译： 光掩模能够防止污点缺陷，以及使用实现相同能力的光掩模制造液晶显示装置的方法。 光掩模包括被配置为透射紫外光的透明基板和被构造为在透明基板的表面上阻挡紫外光的遮光层。 遮光层包括吸收紫外线的吸收层。

公开(公告)号：US08174019B2

公开(公告)日：2012-05-08

申请号：US12392059

申请日：2009-02-24

申请人： Han-Na Ma ,  Ji-Yong Park ,  Jin-Suk Park ,  Gyung-Soon Park

发明人： Han-Na Ma ,  Ji-Yong Park ,  Jin-Suk Park ,  Gyung-Soon Park

IPC分类号： H01L27/14

CPC分类号： H01L27/1255 ,  H01L27/0248

摘要： A display apparatus includes a thin film transistor having a top-gate structure and a storage capacitor that are arranged on a first substrate. An upper electrode of the storage capacitor has a size larger than a size of a lower electrode, so as to cover an entire surface of the lower electrode in a plan view. Thus, electric field caused by static electricity may be prevented from accumulating at a corner of the upper electrode when the electric filed flows from the lower electrode to the upper electrode, thereby preventing an intermediate insulating layer from being burnt.

摘要翻译： 显示装置包括布置在第一基板上的具有顶栅结构的薄膜晶体管和存储电容器。 存储电容器的上电极具有比下电极尺寸大的尺寸，以便在俯视图中覆盖下电极的整个表面。 因此，当电场从下电极流到上电极时，可以防止由静电引起的电场积聚在上电极的拐角处，从而防止中间绝缘层燃烧。

公开(公告)号：US08113609B2

公开(公告)日：2012-02-14

申请号：US12516265

申请日：2007-01-22

申请人： Ji-Yong Park

发明人： Ji-Yong Park

IPC分类号： A47B96/04

CPC分类号： F25D23/067 ,  F25D25/024

摘要： A guide rail for a refrigerator includes a rail body having a back face to be brought into close contact with a side surface of an inner case defining a storage space of the refrigerator; a guide portion provided in the rail body so that the guide portion extends in front of a guide rib formed to be elongated in a fore and aft direction on the side surface of the inner case, thereby guiding the movement of a receiving container to be accommodated in or taken out from the storage space; and a seating space provided in the rail body so that a portion of the guide rib is inserted into the seating space when the back face of the rail body is brought into close contact with the side surface of the inner case.

摘要翻译： 一种用于冰箱的导轨包括：轨道体，其具有与限定冰箱的存储空间的内壳体的侧表面紧密接触的背面; 引导部，其设置在所述导轨体中，使得所述引导部在所述内侧壳体的所述侧面的前后方向上延伸，所述引导肋在所述引导肋的前后方向上形成为沿前后方向延伸，从而引导容纳容纳体的移动 从储存空间进入或取出; 以及设置在轨道体中的座位空间，使得当轨道体的背面与内壳体的侧表面紧密接触时，引导肋的一部分插入到座位空间中。

公开(公告)号：US07297980B2

公开(公告)日：2007-11-20

申请号：US10779781

申请日：2004-02-18

申请人： Ji-Yong Park ,  Ul-Ho Lee ,  Jae-Bon Koo ,  Ki-Yong Lee ,  Hye-Hyang Park

发明人： Ji-Yong Park ,  Ul-Ho Lee ,  Jae-Bon Koo ,  Ki-Yong Lee ,  Hye-Hyang Park

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L29/78696 ,  G02F1/13454 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

摘要： The present invention relates to a flat panel display device comprising a polycrystalline silicon thin film transistor and provides a flat panel display device having improved characteristics by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a driving circuit portion and active channel regions of pixel portion. This may be achieved by having a different number of grain boundaries included in the polycrystalline silicon thin film formed in active channel regions of a switching thin film transistor and a driving thin film transistor formed in the pixel portion, and by having a different number of grain boundaries included in polycrystalline silicon thin film formed in active channel regions of a thin film transistor for driving the pixel portion for each red, green and blue of the pixel portion. Further, this may be achieved by having a different number of grain boundaries included in polycrystalline silicon formed in active channel regions of an NMOS thin film transistor and a PMOS thin film transistor for forming CMOS transistor used in flat panel display device, thereby constructing a thin film transistor to obtain the improved characteristics for each transistor.

摘要翻译： 本发明涉及一种包括多晶硅薄膜晶体管的平板显示装置，通过在驱动电路的有源沟道区域中形成的多晶硅薄膜中包含不同数量的晶界，提供具有改进特性的平板显示装置 像素部分和有源沟道区域。 这可以通过在形成在像素部分中的开关薄膜晶体管和驱动薄膜晶体管的有源沟道区域中形成的多晶硅薄膜中包含不同数量的晶界，并且通过具有不同数量的晶粒来实现 包括在形成在用于驱动像素部分的每个红，绿和蓝的像素部分的薄膜晶体管的有源沟道区域中的多晶硅薄膜中的边界。 此外，这可以通过在NMOS薄膜晶体管的有源沟道区域中形成的多晶硅中包含不同数量的晶界和用于形成用于平板显示器件的CMOS晶体管的PMOS薄膜晶体管来实现，从而构造薄的 以获得每个晶体管的改进特性。