公开(公告)号：US20170271335A1

公开(公告)日：2017-09-21

申请号：US15615643

申请日：2017-06-06

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil YANG ,  SANGSU KIM ,  TaeYong KWON ,  SUNG GI HUR

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US20160372474A1

公开(公告)日：2016-12-22

申请号：US15249518

申请日：2016-08-29

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil YANG ,  SANGSU KIM ,  TaeYong KWON ,  SUNG GI HUR

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

Abstract translation: 制造半导体器件的方法包括制备包括第一区域和第二区域的衬底，在第一和第二区域上依次形成第一半导体层和第二半导体层，图案化第一和第二半导体层以形成下部半导体 图案和上半导体图案，选择性地去除第二区域上的下半导体图案以形成间隙区域，以及分别在第一和第二区域形成栅电极。

公开(公告)号：US20170040323A1

公开(公告)日：2017-02-09

申请号：US15298288

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan LEE ,  SANGSU KIM

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract translation: 半导体器件可以包括设置在基板上以容纳硅锗的应变松弛缓冲层，设置在应变松弛缓冲层上的半导体图案，以包括源区域，漏极区域和将源极区域与漏极连接的沟道区域 区域，以及包围沟道区并在衬底和沟道区之间延伸的栅电极。 源极和漏极区域可以含有浓度为30at％或更高的锗。