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公开(公告)号:US20220037495A1
公开(公告)日:2022-02-03
申请号:US17209290
申请日:2021-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: MYUNG GIL KANG , DONG WON KIM , WOO SEOK PARK , KEUN HWI CHO , SUNG GI HUR
IPC: H01L29/423 , H01L27/092 , H01L29/786 , H01L29/06
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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公开(公告)号:US20170271335A1
公开(公告)日:2017-09-21
申请号:US15615643
申请日:2017-06-06
Applicant: Samsung Electronics Co. Ltd.
Inventor: Junggil YANG , SANGSU KIM , TaeYong KWON , SUNG GI HUR
IPC: H01L27/092 , H01L21/306 , H01L21/8238 , H01L29/10 , H01L29/423
CPC classification number: H01L27/0924 , H01L21/30604 , H01L21/30612 , H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L29/1054 , H01L29/42392
Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.
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公开(公告)号:US20160372474A1
公开(公告)日:2016-12-22
申请号:US15249518
申请日:2016-08-29
Applicant: Samsung Electronics Co. Ltd.
Inventor: Junggil YANG , SANGSU KIM , TaeYong KWON , SUNG GI HUR
IPC: H01L27/092 , H01L21/306 , H01L21/8238
CPC classification number: H01L27/0924 , H01L21/30604 , H01L21/30612 , H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L29/1054 , H01L29/42392
Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.
Abstract translation: 制造半导体器件的方法包括制备包括第一区域和第二区域的衬底,在第一和第二区域上依次形成第一半导体层和第二半导体层,图案化第一和第二半导体层以形成下部半导体 图案和上半导体图案,选择性地去除第二区域上的下半导体图案以形成间隙区域,以及分别在第一和第二区域形成栅电极。
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公开(公告)号:US20250072053A1
公开(公告)日:2025-02-27
申请号:US18947664
申请日:2024-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: MYUNG GIL KANG , DONG WON KIM , WOO SEOK PARK , KEUN HWI CHO , SUNG GI HUR
IPC: H01L29/423 , H01L27/092 , H01L29/06 , H01L29/786
Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.
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