公开(公告)号：US20250072053A1

公开(公告)日：2025-02-27

申请号：US18947664

申请日：2024-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  DONG WON KIM ,  WOO SEOK PARK ,  KEUN HWI CHO ,  SUNG GI HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20220037495A1

公开(公告)日：2022-02-03

申请号：US17209290

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  DONG WON KIM ,  WOO SEOK PARK ,  KEUN HWI CHO ,  SUNG GI HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20180261668A1

公开(公告)日：2018-09-13

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG GIL YANG ,  SEUNG MIN SONG ,  SUNG MIN KIM ,  WOO SEOK PARK ,  GEUM JONG BAE ,  DONG IL BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78645

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.