公开(公告)号：US20250142894A1

公开(公告)日：2025-05-01

申请号：US18752024

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huije RYU ,  Junyoung KWON ,  Changhyun KIM ,  Minsu SEOL

IPC: H01L29/786 ,  H01L21/3115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device may include a two-dimensional (2D) material layer extending in a first direction, a source electrode and a drain electrode each electrically connected to the 2D material layer, an insulating layer arranged on the 2D material layer, and a gate electrode arranged apart from the 2D material layer in a second direction perpendicular to the first direction, wherein the insulating layer includes a dopant.

公开(公告)号：US20250126864A1

公开(公告)日：2025-04-17

申请号：US19001779

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Minsu SEOL ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Hyuntae HWANG ,  Changseok LEE ,  Seongin YOON

IPC: H10D62/82 ,  H01L21/02 ,  H10D48/36 ,  H10D62/80 ,  H10D62/85

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

公开(公告)号：US20240304622A1

公开(公告)日：2024-09-12

申请号：US18416403

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO

Inventor： Minsu SEOL ,  Ce LIANG ,  Jiwoong PARK ,  Kyung-Eun BYUN ,  Changhyun KIM

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L27/092 ,  H01L21/02568 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7606

Abstract: Provided are a semiconductor device including a two-dimensional material and a method of manufacturing the semiconductor device. The semiconductor device may include a substrate, first and second two-dimensional material layers on the substrate and junctioned to each other in a lateral direction to form a coherent interface, a first source electrode and a first drain electrode on the first two-dimensional material layer, a first gate electrode between the first source electrode and the first drain electrode, a second source electrode and a second drain electrode on the second two-dimensional material layer, and a second gate electrode between the second source electrode and the second drain electrode.

公开(公告)号：US20240234583A1

公开(公告)日：2024-07-11

申请号：US18397325

申请日：2023-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7869

Abstract: Provided are a semiconductor device including a two-dimensional (2D) material and an electronic device including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a channel portion, and an extension portion on both sides of the channel portion, a source electrode and a drain electrode respectively on both sides of the channel layer, a gate electrode surrounding the channel portion, a first insulating layer between the channel portion of the channel layer and the gate electrode, and a second insulating layer on the extension portion of the channel layer. The second insulating layer may include a different material than a material of the first insulating layer. The second insulating layer may include a n-type dopant or p-type dopant. A dopant in the extension portion may be the same as a dopant in the second insulating layer.

公开(公告)号：US20240222524A1

公开(公告)日：2024-07-04

申请号：US18507905

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0603 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided are a field effect transistor, a method of manufacturing the field effect transistor, and an electronic device and an electronic apparatus each including the field effect transistor. The field effect transistor includes a channel layer disposed on a substrate, a high-k gate insulating layer disposed on the channel layer, a first composite electrode layer connected to a first side of the channel layer, a second composite electrode layer connected to a second side of the channel layer, and a gate electrode layer disposed on the gate insulating layer. At least one of the first and second composite electrode layers includes a contact resistance reducing layer in contact with the channel layer and a conductive layer in contact with the contact resistance reducing layer. The conductive layer is spaced apart from the channel layer.

公开(公告)号：US20240178307A1

公开(公告)日：2024-05-30

申请号：US18518729

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sungil PARK ,  Jaehyun PARK ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Junyoung KWON ,  Minseok YOO

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/78391

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

公开(公告)号：US20240113028A1

公开(公告)日：2024-04-04

申请号：US18471715

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Yeonchoo CHO ,  Elise BRUTSCHEA ,  Hongkun PARK ,  Minsu SEOL

IPC: H01L23/532 ,  H01L23/528 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/53266 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53252 ,  H01L29/45 ,  H01L29/4908

Abstract: An interconnection layer structure including a two-dimensional (2D) material, an electronic device including the interconnection layer structure, and an electronic apparatus including the electronic device are disclosed. The interconnection layer structure may include a first interconnection layer, and a work function modulation layer directly on one surface of the first interconnection layer. The first interconnection layer may include a metal layer, and the work function modulation layer may be a two-dimensional (2D) material layer that includes ruthenium (Ru).

公开(公告)号：US20240038903A1

公开(公告)日：2024-02-01

申请号：US18483058

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Hyeonjin SHIN ,  Minseok YOO ,  Minhyun LEE

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/45 ,  H01L29/0665 ,  H01L21/02417 ,  H01L21/02568 ,  H01L21/823412 ,  H01L29/1606

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US20240021676A1

公开(公告)日：2024-01-18

申请号：US18331463

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Minsu SEOL ,  Junyoung KWON ,  Keunwook SHIN ,  Minseok YOO

IPC: H01L29/18 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H10B10/00 ,  H10B43/27

CPC classification number: H01L29/18 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H10B10/125 ,  H10B43/27

Abstract: A semiconductor device includes a channel including a two-dimensional (2D) semiconductor material, a source electrode and a drain electrode electrically connected to opposite sides of the channel, respectively, a transition metal oxide layer on the channel and including a transition metal oxide, a dielectric layer on the transition metal oxide layer and including a high-k material, and a gate electrode on the dielectric layer.

公开(公告)号：US20220077321A1

公开(公告)日：2022-03-10

申请号：US17370480

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/76 ,  H01L21/02 ,  H01L29/66

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.