Substrate transfer system
    1.
    发明授权

    公开(公告)号:US11984338B2

    公开(公告)日:2024-05-14

    申请号:US17745595

    申请日:2022-05-16

    CPC classification number: H01L21/6773 B66C19/00 H01L21/67736

    Abstract: A substrate transfer system capable of performing efficient distribution exchange between fabricating facilities is provided. The substrate transfer system includes a lower rail, an upper rail which is located above the lower rail from a ground plane, and extends to be parallel to the lower rail, a conveyor which extends to intersect the lower rail and the upper rail, below the lower rail, a first lower transport unit which transports a first carrier along the lower rail and unloads the first carrier onto the conveyor, and a first upper transport unit which transports a second carrier along the upper rail and unloads the second carrier onto the conveyor, wherein the conveyor includes a linear module which moves the first carrier and the second carrier in a linear direction, and a turning module which turns the first carrier and the second carrier.

    Substrate analysis apparatus and substrate analysis method

    公开(公告)号:US11982705B2

    公开(公告)日:2024-05-14

    申请号:US17690317

    申请日:2022-03-09

    CPC classification number: G01R31/2831 H01L21/6735 H01L21/6773

    Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

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