公开(公告)号：US20240006215A1

公开(公告)日：2024-01-04

申请号：US18195757

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hyuk PARK ,  Youn Gon Oh ,  Hyuk Kwon ,  Young-Kyu Kim ,  Ji Hun Kim ,  Sung-Hoon Lee ,  Jeong Kwan Jung

IPC: H01L21/677

CPC classification number: H01L21/67733 ,  H01L21/67769 ,  H01L21/6773 ,  H01L21/67706 ,  H01L21/67736

Abstract: A wafer storage and transport system includes a ceiling surface which includes a first surface and a second surface, a first traveling rail installed on the second surface, a second traveling rail which is spaced apart from the first surface in a third direction, and extends in a first direction, a transport unit which is movable in the first direction along the second traveling rail and transports a FOUP, storage spaces installed on the first surface and which may store the FOUP, an interface port installed on the second surface and which temporarily stores the FOUP, and an OHT which is movable along the first traveling rail, wherein the transport unit grasps the FOUP arranged in the storage spaces and transports the FOUP to the interface port, and the OHT grasps the FOUP temporarily stored in the interface port and transports the FOUP to a semiconductor facility.

公开(公告)号：US09285415B2

公开(公告)日：2016-03-15

申请号：US14084224

申请日：2013-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kwon ,  Hyoung-Young Lee ,  Sang-Go Han

IPC: G01R31/26 ,  G01R31/319

CPC classification number: G01R31/2601 ,  G01R31/31908 ,  G01R31/31926

Abstract: A built-off test (BOT) device includes a signal processing block, an output selection block and a signal control block. The signal processing block duplicates a test signal to apply a plurality of duplicated test signals to each of a plurality of devices under test (DUTs) through each of corresponding channels, and the signal processing block provides a plurality of decision signals based upon a plurality of test result signals received from each of the DUTs. The output selection block merges the decision signals as a final decision signal or sequentially outputs the decision signals as the final decision signal, in response to an output mode selection signal. The signal control block provides the test signal to the signal processing block or provides the final decision signal externally, in response to a first switching control signal.