公开(公告)号：US20190139899A1

公开(公告)日：2019-05-09

申请号：US16240174

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US20160172291A1

公开(公告)日：2016-06-16

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk KIM ,  HyunJong MOON ,  Tai-Hyun EUM ,  Heeseok LEE ,  Keung Beum KIM ,  Yonghoon KIM ,  Yoonha JUNG ,  Seung-Yong CHA

IPC: H01L23/498 ,  H01L23/34

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

Abstract translation: 半导体封装可以包括具有顶表面和与顶表面相对的底表面的封装衬底，封装衬底的顶表面被配置为具有安装在其上的半导体芯片，封装衬底中的功率块和接地块， 所述功率块被配置为穿过所述封装衬底的电力通路，并且所述接地块被配置为穿过所述封装衬底的接地路径，从所述功率块和所述接地块延伸的第一通孔以及电连接到所述半导体芯片的所述第一通孔， 第二通孔从功率块和接地块延伸到封装衬底的底表面，并且阻挡通孔以穿透功率块和接地块，块通孔电连接到半导体芯片并与功率块电分离， 地块。

公开(公告)号：US20160329285A1

公开(公告)日：2016-11-10

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.