公开(公告)号：US20160135326A1

公开(公告)日：2016-05-12

申请号：US14820784

申请日：2015-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-young KIM

IPC: H05K7/20 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/181 ,  H01L23/48 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/0298 ,  H05K1/113 ,  H05K3/4038 ,  H05K3/4084 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided is a printed circuit board including a first conductive layer including a first conductive layer including a recessed portion, a protruding portion disposed at a higher level than that of the recessed portion, and a connecting portion connecting the recessed portion with the protruding portion. A second conductive layer is disposed above the recessed portion of the first conductive layer. A core layer is disposed between the first conductive layer and the second conductive layer. An upper solder resist layer is disposed on the second conductive layer. The upper solder resist layer exposes at least a portion of the protruding portion. A lower solder resist layer is disposed below the first conductive layer.

Abstract translation: 提供了一种印刷电路板，包括：第一导电层，包括第一导电层，第一导电层包括凹部，突出部分设置在比凹部更高的位置;以及连接部分，其将凹部与突出部分连接。 第二导电层设置在第一导电层的凹部的上方。 芯层设置在第一导电层和第二导电层之间。 上部阻焊层设置在第二导电层上。 上部阻焊层暴露突出部分的至少一部分。 下部阻焊层设置在第一导电层的下方。

公开(公告)号：US20210183818A1

公开(公告)日：2021-06-17

申请号：US17169701

申请日：2021-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-young KIM

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

公开(公告)号：US20180277474A1

公开(公告)日：2018-09-27

申请号：US15994004

申请日：2018-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： MuSeob SHIN ,  Won-young KIM ,  Sanghyun PARK ,  Jinchan AHN

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

公开(公告)号：US20240186293A1

公开(公告)日：2024-06-06

申请号：US18422778

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-young KIM

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

公开(公告)号：US20180358328A1

公开(公告)日：2018-12-13

申请号：US15855205

申请日：2017-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SunWon KANG ,  Won-young KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5226 ,  H01L24/05 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06572

Abstract: A semiconductor package includes a first interconnect substrate on a first redistribution substrate and having a first opening penetrating the first interconnect substrate. A first semiconductor chip is on the first redistribution substrate and the first opening of the first interconnect substrate. A second redistribution substrate is on the first interconnect substrate and the first semiconductor chip. A second interconnect substrate is on the second redistribution substrate and has a second opening penetrating the second interconnect substrate. A second semiconductor chip is on the second redistribution substrate and in the second opening of the second interconnect substrate.

公开(公告)号：US20140230868A1

公开(公告)日：2014-08-21

申请号：US13930563

申请日：2013-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chong-joon RYU ,  Seung-hyun HONG ,  Won-young KIM ,  Seung-hyun BAIK ,  Sang-hoon LEE ,  Jae-young CHOI

IPC: H01L35/22

CPC classification number: H01L35/22

Abstract: A composite laminate may include graphene and a thermoelectric inorganic material including a single crystal having a hexagonal crystal system.

Abstract translation: 复合层叠体可以包括石墨烯和包括具有六方晶系晶体的单晶的热电无机材料。

公开(公告)号：US20190237431A1

公开(公告)日：2019-08-01

申请号：US16214397

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-young KIM

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

公开(公告)号：US20190115235A1

公开(公告)日：2019-04-18

申请号：US16140877

申请日：2018-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-chan AHN ,  Won-young KIM ,  Kyung-seon HWANG

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L23/544 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.

公开(公告)号：US20140182646A1

公开(公告)日：2014-07-03

申请号：US14096560

申请日：2013-12-04

Applicant: Sungkyunkwan University Foundation for Corporate Collaboration ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-young CHOI ,  Seung-hyun BAIK ,  Won-young KIM ,  Dae-woo SUH ,  Sang-hoon LEE ,  Seung-hyun HONG

IPC: H01L35/26

CPC classification number: H01L35/26 ,  B82Y99/00 ,  H01L35/02 ,  H01L35/12 ,  H01L35/14 ,  H01L35/16 ,  H01L35/18 ,  H01L35/24 ,  Y10S977/742 ,  Y10S977/948

Abstract: A thermoelectric material includes a stack structure including alternately stacked first and second material layers. The first material layer may include a carbon nano-material. The second material layer may include a thermoelectric inorganic material. The first material layer may include a thermoelectric inorganic material in addition to the carbon nano-material. The carbon nano-material may include, for example, graphene. At least one of the first and second material layers may include a plurality of nanoparticles. The thermoelectric material may further include at least one conductor extending in an out-of-plane direction of the stack structure.

Abstract translation: 热电材料包括堆叠结构，其包括交替堆叠的第一和第二材料层。 第一材料层可以包括碳纳米材料。 第二材料层可以包括热电无机材料。 除了碳纳米材料之外，第一材料层可以包括热电无机材料。 碳纳米材料可以包括例如石墨烯。 第一和第二材料层中的至少一个可以包括多个纳米颗粒。 热电材料还可以包括沿堆叠结构的平面外方向延伸的至少一个导体。

公开(公告)号：US20130167897A1

公开(公告)日：2013-07-04

申请号：US13729820

申请日：2012-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-young CHOI ,  Seung-hyun BAIK ,  Seung-hyun HONG ,  Won-young KIM ,  Eun-sung KIM ,  Young-hee LEE

IPC: H01L35/22 ,  H01L35/18 ,  H01L35/34 ,  H01L35/16

CPC classification number: H01L35/22 ,  C01B32/184 ,  H01L35/16 ,  H01L35/32 ,  H01L35/34 ,  Y02P20/133

Abstract: A heterogeneous laminate including: graphene; and a thermoelectric inorganic compound disposed on the graphene.

Abstract translation: 异质层压板包括：石墨烯; 以及设置在石墨烯上的热电无机化合物。