公开(公告)号：US10141372B2

公开(公告)日：2018-11-27

申请号：US15067833

申请日：2016-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US09570400B2

公开(公告)日：2017-02-14

申请号：US14573134

申请日：2014-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Na Baek ,  Seok-Won Lee ,  Eun-Seok Cho ,  Dong-Han Kim ,  Kyoung-Sei Choi ,  Sa-Yoon Kang

IPC: H01L23/373 ,  H01L23/538 ,  H01L23/14 ,  H01L23/522 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Abstract translation: 提供半导体封装，包括半导体芯片; 半导体芯片上的上部结构，上部结构具有第一热膨胀系数; 以及在所述半导体芯片下方的下部结构，所述下部结构具有小于或等于所述第一热膨胀系数的第二热膨胀系数。

公开(公告)号：US20140363923A1

公开(公告)日：2014-12-11

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US08890294B2

公开(公告)日：2014-11-18

申请号：US13771609

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US20200273912A1

公开(公告)日：2020-08-27

申请号：US15931089

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11519 ,  H01L27/06 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11548

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US10483323B2

公开(公告)日：2019-11-19

申请号：US16178860

申请日：2018-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US20190081105A1

公开(公告)日：2019-03-14

申请号：US16178860

申请日：2018-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/06 ,  H01L27/11582 ,  H01L27/11519

CPC classification number: H01L27/2481 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US20130328177A1

公开(公告)日：2013-12-12

申请号：US13771609

申请日：2013-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L21/56 ,  H01L23/552

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US10825865B2

公开(公告)日：2020-11-03

申请号：US16804810

申请日：2020-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joyoung Park ,  Seok-Won Lee ,  Seongjun Seo

IPC: H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/06

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

公开(公告)号：US10026749B2

公开(公告)日：2018-07-17

申请号：US15349084

申请日：2016-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jaeshin Park ,  Joyoung Park ,  Jiwoong Sue ,  Seok-Won Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.