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公开(公告)号：US20190080770A1
公开(公告)日：2019-03-14
申请号：US16186840
申请日：2018-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-ho SONG , Se-heon BAEK , Yong-sung CHO
Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
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公开(公告)号：US20180137920A1
公开(公告)日：2018-05-17
申请号：US15495072
申请日：2017-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-ho SONG , Se-heon BAEK , Yong-sung CHO
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/12 , G11C16/26 , G11C16/30 , G11C2211/5642
Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
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公开(公告)号：US20170287561A1
公开(公告)日：2017-10-05
申请号：US15383408
申请日：2016-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： YO-HAN LEE , Ji-suk KIM , Chang-yeon YU , Jin-young CHUN , Se-heon BAEK , Jun-young KO , Seong-ook JUNG , Ji-su KIM
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/24 , G11C16/3459
Abstract: A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.
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公开(公告)号：US20170278579A1
公开(公告)日：2017-09-28
申请号：US15383132
申请日：2016-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： YO-HAN LEE , Ji-suk KIM , Chang-yeon YU , Jin-young CHUN , Se-heon BAEK , Jun-young KO , Seong-ook JUNG , Ji-su KIM
CPC classification number: G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/28
Abstract: A data read operation method of a memory device includes applying a read voltage having a first preparation level and a first target level to a word line of a selected cell in the memory device to read a program state of the selected cell, applying a first read pass voltage having a second preparation level and a second target level to at least one word line of first non-selected cells not adjacent to the selected cell and in the same string as the selected cell, and applying a second read pass voltage having a third target level to a word line of at least one second non-selected cell adjacent to the selected cell.
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