公开(公告)号：US20230162784A1

公开(公告)日：2023-05-25

申请号：US17881187

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmyung KANG ,  Hoyoung TANG ,  Inhak LEE ,  Sangyeop BAECK ,  Dongwook SEO

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074

Abstract: A memory device includes a bit cell array including a plurality of bit cells connected to a first auxiliary line to which a cell power voltage is supplied; a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the bit cell array during a write operation; and a write auxiliary circuit connected to the first auxiliary line and a second auxiliary line extending in parallel to the first auxiliary line, and configured to lower a cell power voltage for a first bit cell spaced apart from the write driver during the write operation, wherein the cell power voltage is supplied to the first auxiliary line through the second auxiliary line, and in sequence from the first bit cell to a second bit cell adjacent to the write driver through the first auxiliary line.

公开(公告)号：US20220037339A1

公开(公告)日：2022-02-03

申请号：US17371522

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak LEE ,  Seunghun LEE ,  Sangyeop BAECK ,  Seunghan PARK ,  Hyejin LEE

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  G11C11/417

Abstract: An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.

公开(公告)号：US20230144938A1

公开(公告)日：2023-05-11

申请号：US18052412

申请日：2022-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak LEE ,  Sangyeop BAECK ,  Jaesung CHOI

IPC: G11C5/06 ,  H01L23/522 ,  G11C11/412 ,  H01L23/528

CPC classification number: G11C5/06 ,  H01L23/5226 ,  G11C11/412 ,  H01L23/5283

Abstract: An integrated circuit includes is provided. The integrated circuit includes: a plurality of bit lines spaced apart from each other along a first direction and extending in a second direction perpendicular to the first direction through a first sub-array and a second sub-array neighboring the first sub-array in the second direction. Each of the plurality of bit lines includes: a first metal wiring extending in the second direction, the first metal wiring including a first portion and a second portion that is separated from the first portion by a first cutting portion; a third metal wiring extending in the second direction, and at least partially overlapping the first metal wiring along a third direction perpendicular to the first direction and the second direction; and two bridges electrically connecting the first metal wiring to the third metal wiring.