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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12272606B2

    公开(公告)日：2025-04-08

    申请号：US18300983

    申请日：2023-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangmin Yoo ,  Juyoun Kim ,  Hyungjoo Na ,  Bongseok Suh ,  Jooho Jung ,  Euichul Hwang ,  Sungmoon Lee

    IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/118

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

    PHASE-LOCKED LOOP CIRCUIT, PHASE ERROR SIGN GENERATOR AND RFIC
    3.
    发明申请
    PHASE-LOCKED LOOP CIRCUIT, PHASE ERROR SIGN GENERATOR AND RFIC 有权

    公开(公告)号：US20250070790A1

    公开(公告)日：2025-02-27

    申请号：US18808348

    申请日：2024-08-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minseob Lee ,  Sangmin Yoo ,  Joonhee Lee ,  Ikkyun Jo ,  Honggul Han

    IPC: H03L7/197 ,  H03L7/097 ,  H03L7/099

    Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

    AMPLIFIER CAPABLE OF CANCELING LEAKAGE COMPONENTS
    5.
    发明公开
    AMPLIFIER CAPABLE OF CANCELING LEAKAGE COMPONENTS 审中-公开

    公开(公告)号：US20240120884A1

    公开(公告)日：2024-04-11

    申请号：US18216766

    申请日：2023-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghyun Yoon ,  Jeongyeol Bae ,  Jongsoo Lee ,  Sangmin Yoo

    IPC: H03F1/02 ,  H03F3/45

    CPC classification number: H03F1/0205 ,  H03F3/45269 ,  H03F2200/451

    Abstract: Disclosed is an amplifier that includes a first-first (1-1) transistor and a first-second (1-2) transistor to which differential input signals are applied to gate terminals, respectively; a second-first (2-1) transistor including: one end connected to the 1-1 transistor, a gate terminal configured to receive an operating signal, and the other end configured to output one of differential output signals; a second-second (2-2) transistor including: one end connected to the 1-2 transistor, a gate terminal configured to receive the operating signal, and the other end configured to output the other one of the differential output signals; and a switch connected to one end of the 1-1 transistor and one end of the 1-2 transistor. The switch is configured to turn on based on the 1-1 transistor, the 1-2 transistor, the 2-1 transistor, and the 2-2 transistor being turned off.

    CMOS CHIP AND ELECTRONIC DEVICE INCLUDING THE CMOS CHIP
    7.
    发明公开
    CMOS CHIP AND ELECTRONIC DEVICE INCLUDING THE CMOS CHIP 审中-公开

    公开(公告)号：US20230308123A1

    公开(公告)日：2023-09-28

    申请号：US18063301

    申请日：2022-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmin KIM ,  Hongjong Park ,  Sangmin Yoo ,  Sangwook Han

    IPC: H04B1/04 ,  H04B1/18 ,  H03H7/38

    CPC classification number: H04B1/0458 ,  H03H7/38 ,  H04B1/0483 ,  H04B1/18

    Abstract: A CMOS chip includes a signal converting circuit configured to convert a baseband signal and an RF signal, a plurality of ports through which the RF signal is transmitted or received, the plurality of ports being respectively included in a first transmission path, a second transmission path, and a reception path, and a plurality of matching networks connected to the signal converting circuit, the plurality of matching networks being respectively connected to the plurality of ports, a first matching network among the plurality of matching networks including an external matching network, and the external matching network being configured to perform an impedance matching of a compound semiconductor device.

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