公开(公告)号：US20210119649A1

公开(公告)日：2021-04-22

申请号：US16796201

申请日：2020-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungjoong Kang ,  Jungwoo Kim ,  Pilsung Jang

IPC: H04B1/00 ,  H03F3/195 ,  H04B7/0413

Abstract: A radio-frequency integrated chip (RFIC) is described which provides a number of low noise amplifiers (LNAs) and load circuits. The low noise amplifiers are organized in groups. In some embodiments, a load circuit may be dedicated to a group or shared between groups. The RFIC includes an LNA group including a plurality of LNAs configured to amplify carrier signals related to a plurality of frequency bands, a second LNA group configured to amplify a plurality of second carrier signals, a first load circuit group dedicated to the first LNA group, a second load circuit group dedicated to the second LNA group, and a third load circuit group shared between the first LNA group and the second LNA group. In some embodiments the third load circuit group adaptively performs frequency down-conversion on a carrier signal amplified by at least one of the first LNA group and the second LNA group.

公开(公告)号：US11228326B2

公开(公告)日：2022-01-18

申请号：US16796201

申请日：2020-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungjoong Kang ,  Jungwoo Kim ,  Pilsung Jang

IPC: H04B1/00 ,  H03F3/195 ,  H04B7/0413

Abstract: A radio-frequency integrated chip (RFIC) is described which provides a number of low noise amplifiers (LNAs) and load circuits. The low noise amplifiers are organized in groups. In some embodiments, a load circuit may be dedicated to a group or shared between groups. The RFIC includes an LNA group including a plurality of LNAs configured to amplify carrier signals related to a plurality of frequency bands, a second LNA group configured to amplify a plurality of second carrier signals, a first load circuit group dedicated to the first LNA group, a second load circuit group dedicated to the second LNA group, and a third load circuit group shared between the first LNA group and the second LNA group. In some embodiments the third load circuit group adaptively performs frequency down-conversion on a carrier signal amplified by at least one of the first LNA group and the second LNA group.

公开(公告)号：US20250080069A1

公开(公告)日：2025-03-06

申请号：US18788743

申请日：2024-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyong Yoo ,  Beomyu Park ,  Byoungjoong Kang ,  Jeongyeol Bae ,  Bosung Suh ,  Sangmin Yoo ,  Jongsoo Lee

IPC: H03F3/26 ,  H03F1/30 ,  H03F1/56 ,  H03F3/24

Abstract: A unit amplification circuit includes a push-pull circuit having a transistor with a gate connected to an input terminal, a symmetrical circuit connected symmetrically to the push-pull circuit and configured to be turned off in a first operation mode and turned on in a second operation mode, and a path control circuit connected to a drain of the transistor and configured to connect the drain and an output terminal in the first operation mode and to disconnect the drain and the output terminal in the second operation mode.

公开(公告)号：US11252728B2

公开(公告)日：2022-02-15

申请号：US16915443

申请日：2020-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungjoong Kang ,  Heeseon Shin

IPC: H04B7/0413 ,  H04W72/04

Abstract: A receiver including a plurality of primary antennas configured to receive a plurality of first carrier signals corresponding to at least a first frequency band; a plurality of diversity antennas configured to receive a plurality of second carrier signals corresponding to at least a second frequency band; a first local oscillator configured to generate a first oscillation signal; a first load circuit pair connected to the first local oscillator, and configured to frequency down-convert at least one of the plurality of first carrier signals, and having a first load circuit and a second load circuit adjacent to the first load circuit; and a second load circuit pair connected to the first local oscillator, configured to frequency down-convert at least of the plurality of second carrier signals, and having a third load circuit and a fourth load circuit adjacent to the third load circuit.